| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_max_throughput_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_err_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| rom_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| passthru_mem_tl_intg_err | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_fsm_local_esc | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_digest | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_local_esc | 0 | 2 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_mem_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 20 test runs | |||
| rom_ctrl_smoke | 1217059429186215857282036739020012623611497462236890280521415978790580436633 | None | ||
| rom_ctrl_stress_all | 110027855555860329805553031408803984002120152637997586724155742877991580716811 | None | ||
| rom_ctrl_max_throughput_chk | 96839251284931712543241506662528992628885607063138364196377703627849592522463 | None | ||
| rom_ctrl_corrupt_sig_fatal_chk | 76123104121864677956800982400417656814601215405390902476004934832274184285247 | None | ||
| rom_ctrl_kmac_err_chk | 70896383550225067593118362728125130962632909632336493985300909994465808941080 | None | ||
| rom_ctrl_stress_all_with_rand_reset | 80040828285452185354712415270574881053678123406135743450099841440006576441682 | None | ||
| rom_ctrl_sec_cm | 101829173796674495653696049781018126063410722585183121349750136109835083730921 | None | ||
| rom_ctrl_passthru_mem_tl_intg_err | 11091302233950556383827548574028999580457117308730901518694295671488052761038 | None | ||
| rom_ctrl_tl_errors | 40960540479736637135041910129058976970089470357893945995374541023688214338205 | None | ||
| rom_ctrl_tl_intg_err | 75322914802493249476920452967435403974764898153706571351738991583180595859840 | None | ||
| rom_ctrl_alert_test | 66808371252149078767176472469463798633671870051668488997274915634974927439370 | None | ||
| rom_ctrl_mem_walk | 111717271720005794783411905039307399816066010461435799158349841261099064785976 | None | ||
| rom_ctrl_mem_partial_access | 41320128109767447405111426868557828080753135672541951523089139430852358947340 | None | ||
| rom_ctrl_csr_hw_reset | 73504623471674498223812734302222181861510680952455620617566944637736773263852 | None | ||
| rom_ctrl_csr_rw | 1964174069532669596336365366396376802937331259650212033251916855911503752854 | None | ||
| rom_ctrl_csr_bit_bash | 70681725401155979543830195100648079453719491582965629547708494991205398710212 | None | ||
| rom_ctrl_csr_aliasing | 35892979815236816141132141814559578695836144518284437062503635765301495393764 | None | ||
| rom_ctrl_same_csr_outstanding | 94390622595281067627072665899619639346548104820505754219607833749930414974329 | None | ||
| rom_ctrl_csr_mem_rw_with_rand_reset | 32621574036918782381673712670029758750937131420921665092901757855649413230596 | None | ||
| rom_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/default/fusesoc-work/185335: No such file or directory.
/tmp/vcs_20260730153154_132863/.stack_annotator_gdb_cmd_file_TSWyJd:2: Error in sourced command file:
No stack.
Process VmPeak: 437116 kb, VmSize: 421512 kb
System Free Memory: 321126984 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 11.741 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/cover_reg_top/fusesoc-work/105167: No such file or directory.
/tmp/vcs_20260730153043_10296/.stack_annotator_gdb_cmd_file_c4ioIK:2: Error in sourced command file:
No stack.
Process VmPeak: 438024 kb, VmSize: 422420 kb
System Free Memory: 320952640 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 12.959 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| rom_ctrl | None | None | ||