Simulation Results: rstmgr

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.31 %
  • code
  • 99.12 %
  • assert
  • 98.53 %
  • func
  • 94.28 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.06 %
  • toggle
  • 99.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.050s 142.275us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.810s 125.203us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.750s 73.949us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.160s 2500.636us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.490s 159.950us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.000s 187.371us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.750s 73.949us 1 1 100.00
rstmgr_csr_aliasing 1.490s 159.950us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.800s 234.194us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.420s 178.160us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.710s 79.148us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.790s 1985.174us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.790s 1985.174us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.790s 1985.174us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.790s 1985.174us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 9.900s 4318.308us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.680s 69.536us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.390s 230.917us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.390s 230.917us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.810s 125.203us 1 1 100.00
rstmgr_csr_rw 0.750s 73.949us 1 1 100.00
rstmgr_csr_aliasing 1.490s 159.950us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 145.281us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.810s 125.203us 1 1 100.00
rstmgr_csr_rw 0.750s 73.949us 1 1 100.00
rstmgr_csr_aliasing 1.490s 159.950us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 145.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 9.620s 8635.644us 1 1 100.00
rstmgr_tl_intg_err 2.340s 936.448us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 9.620s 8635.644us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 9.620s 8635.644us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.340s 936.448us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.020s 194.778us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.990s 2813.429us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.900s 301.360us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 9.620s 8635.644us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.750s 73.949us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.750s 73.949us 1 1 100.00