Simulation Results: rv_timer

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.05 %
  • code
  • 94.34 %
  • assert
  • 98.73 %
  • func
  • 92.06 %
  • line
  • 99.64 %
  • branch
  • 100.00 %
  • cond
  • 99.08 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.130s 594.716us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.630s 14.705us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.570s 68.986us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.830s 333.378us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.790s 38.888us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.020s 27.760us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.570s 68.986us 1 1 100.00
rv_timer_csr_aliasing 0.790s 38.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.630s 129.705us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.720s 754.709us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.790s 905.847us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.790s 905.847us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.700s 4067.398us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 15.852us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.560s 19.618us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.530s 88.406us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.530s 88.406us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 14.705us 1 1 100.00
rv_timer_csr_rw 0.570s 68.986us 1 1 100.00
rv_timer_csr_aliasing 0.790s 38.888us 1 1 100.00
rv_timer_same_csr_outstanding 0.730s 123.887us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.630s 14.705us 1 1 100.00
rv_timer_csr_rw 0.570s 68.986us 1 1 100.00
rv_timer_csr_aliasing 0.790s 38.888us 1 1 100.00
rv_timer_same_csr_outstanding 0.730s 123.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.760s 61.189us 1 1 100.00
rv_timer_tl_intg_err 1.240s 408.447us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.240s 408.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.660s 63.018us 0 1 0.00
max_value 1 1 100.00
rv_timer_max 0.570s 28.092us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 9.070s 8418.916us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 92508734883924859279170811859745430274950707608586289562300763347161103179649 81
UVM_INFO @ 63018207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 72233804014719265402444330492954359556539955391618057272958168458077981900537 80
UVM_INFO @ 129704877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 38865935210289023568581916106697602277193135790486470575917706528223976728724 253
UVM_INFO @ 8418916382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---