Simulation Results: spi_device/1r1w

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.79 %
  • code
  • 93.92 %
  • assert
  • 95.40 %
  • func
  • 74.06 %
  • line
  • 98.86 %
  • branch
  • 98.16 %
  • cond
  • 95.91 %
  • toggle
  • 87.29 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 143.940s 79209.481us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.020s 143.993us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.270s 93.193us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 7.920s 1108.684us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 7.990s 232.183us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.600s 571.390us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.270s 93.193us 1 1 100.00
spi_device_csr_aliasing 7.990s 232.183us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.620s 22.036us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.350s 28.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.700s 18.804us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.670s 2.466us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.650s 3.709us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.240s 237.034us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.240s 237.034us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.160s 2959.639us 1 1 100.00
spi_device_tpm_sts_read 0.690s 295.723us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 29.810s 19448.476us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.510s 565.458us 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 13.990s 44018.002us 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 13.990s 44018.002us 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.070s 848.640us 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.070s 848.640us 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.070s 848.640us 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.070s 848.640us 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.070s 848.640us 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 12.180s 5860.985us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 4.590s 305.757us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 4.590s 305.757us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 4.590s 305.757us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.930s 1851.329us 1 1 100.00
spi_device_read_buffer_direct 6.870s 733.343us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 4.590s 305.757us 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 0.670s 24.458us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 1.620s 45.593us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 1.620s 45.593us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 8.350s 1603.528us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 143.940s 79209.481us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 69.560s 32054.160us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 222.520s 33958.942us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.660s 44.402us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.710s 12.072us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.050s 1416.247us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.050s 1416.247us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 143.993us 1 1 100.00
spi_device_csr_rw 1.270s 93.193us 1 1 100.00
spi_device_csr_aliasing 7.990s 232.183us 1 1 100.00
spi_device_same_csr_outstanding 1.700s 156.501us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 143.993us 1 1 100.00
spi_device_csr_rw 1.270s 93.193us 1 1 100.00
spi_device_csr_aliasing 7.990s 232.183us 1 1 100.00
spi_device_same_csr_outstanding 1.700s 156.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.890s 213.377us 1 1 100.00
spi_device_tl_intg_err 17.080s 935.858us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 17.080s 935.858us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 105609202480336278617426559891332475695409446682956832362014835111373668648477 81
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1891171 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1891171 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[993])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 39305284502920191433199074877552078963410044656214591393834757817743561497209 81
UVM_ERROR @ 932892 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1d4 [111010100] vs 0x0 [0])
UVM_ERROR @ 933892 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x323 [1100100011] vs 0x0 [0])
UVM_ERROR @ 1005892 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x46 [1000110] vs 0x0 [0])
UVM_ERROR @ 1067892 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2c1 [1011000001] vs 0x0 [0])