Simulation Results: sram_ctrl/main

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.68 %
  • code
  • 95.69 %
  • assert
  • 97.96 %
  • func
  • 93.40 %
  • block
  • 96.02 %
  • line
  • 96.75 %
  • branch
  • 94.16 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 357.401us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 87.234us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.897us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 33.883us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.207us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 350.537us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 21.897us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.207us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 202.000s 98410.059us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 48.000s 5744.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 20.000s 16328.498us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 101.000s 3749.437us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 156.000s 72252.050us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 46.000s 46321.122us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 32.000s 22285.711us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 23.000s 11147.916us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 375.005us 1 1 100.00
sram_ctrl_partial_access_b2b 220.000s 8331.627us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 5.000s 3473.885us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 688.524us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 676.016us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 5576.567us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 705.059us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 87.000s 23009.642us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 35.898us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 39.411us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 39.411us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 87.234us 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.897us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.207us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 31.820us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 87.234us 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.897us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.207us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 31.820us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 14765.383us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 613.432us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 244.278us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 613.432us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 244.278us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 5576.567us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 5576.567us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 21.897us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 23.000s 11147.916us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 11147.916us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 11147.916us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 32.000s 22285.711us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 699.012us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 13.000s 14765.383us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 3040.620us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 357.401us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 357.401us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 23.000s 11147.916us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 613.432us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 32.000s 22285.711us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 613.432us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 613.432us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 357.401us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 613.432us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.000s 339.461us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 39332239919388226030316681887673937853970118397109321552082777873747189246983 86
UVM_INFO @ 3473885232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 48580143447083003651286255743639029272531691692602189969765053804668510781164 86
UVM_INFO @ 688524077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 20715066471891831457605718071534358682773441107160139812215819313122689987010 86
UVM_INFO @ 676016014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---