Simulation Results: sram_ctrl/ret

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.70 %
  • code
  • 82.22 %
  • assert
  • 97.67 %
  • func
  • 92.20 %
  • block
  • 93.61 %
  • line
  • 94.83 %
  • branch
  • 89.17 %
  • toggle
  • 78.23 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 621.074us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 20.497us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.560us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 197.525us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 48.486us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 48.405us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 17.560us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 48.486us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 6.000s 1653.643us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 746.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 12.000s 1704.657us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 92.000s 17641.715us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 958.242us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 6.000s 170.460us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 668.232us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 788.538us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 252.205us 1 1 100.00
sram_ctrl_partial_access_b2b 185.000s 31143.407us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 26.893us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 27.941us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 32.779us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 153.993us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 30.504us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 40.000s 15448.407us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 43.214us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 183.617us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 183.617us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 20.497us 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.560us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 48.486us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 37.103us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 20.497us 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.560us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 48.486us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 37.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 396.112us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 903.425us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 116.712us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 903.425us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 116.712us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 153.993us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 153.993us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.560us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 788.538us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 788.538us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 788.538us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 668.232us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 37.030us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 396.112us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 95.408us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 621.074us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 621.074us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 788.538us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 903.425us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 668.232us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 903.425us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 903.425us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 621.074us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 903.425us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 22.000s 2461.245us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 73179036076832573028059963011702576183040685390687305357769287129526559323884 86
UVM_INFO @ 26892659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 47766986603352887747285714651764555025732814783175523994037747604730909939646 86
UVM_INFO @ 27941001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 75260183874752684284103052566163663837178410031275772055269303395277008139496 86
UVM_INFO @ 32778702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---