Simulation Results: sysrst_ctrl

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.17 %
  • code
  • 92.47 %
  • assert
  • 94.73 %
  • func
  • 71.32 %
  • line
  • 97.17 %
  • branch
  • 97.37 %
  • cond
  • 95.46 %
  • toggle
  • 98.63 %
  • FSM
  • 73.72 %
Validation stages
V1
100.00%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.000s 2111.982us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.040s 2463.209us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.530s 2238.176us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.180s 2254.025us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 11.070s 6020.323us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.610s 2076.493us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 94.890s 39232.181us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.630s 2633.112us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.060s 2040.818us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.610s 2076.493us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.630s 2633.112us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 176.780s 101389.606us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 202.540s 123981.138us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 5.980s 3109.918us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 6.400s 3865.034us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.050s 2511.521us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.250s 2146.198us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 4.970s 2757.466us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.950s 2619.771us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 8.240s 403412.307us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 52.840s 34484.730us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 2.040s 11625.487us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.840s 2013.525us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.800s 2014.929us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.430s 2127.376us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.430s 2127.376us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.070s 6020.323us 1 1 100.00
sysrst_ctrl_csr_rw 1.610s 2076.493us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.630s 2633.112us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.610s 7530.776us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 11.070s 6020.323us 1 1 100.00
sysrst_ctrl_csr_rw 1.610s 2076.493us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.630s 2633.112us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.610s 7530.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 31.170s 22014.307us 1 1 100.00
sysrst_ctrl_tl_intg_err 10.740s 22279.717us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 10.740s 22279.717us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 3.680s 15325.932us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  1 test run
sysrst_ctrl_ultra_low_pwr 107686159409192242638027298060945702775754969656790900596348928893905431084828 655
UVM_ERROR @ 403412306921 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 403412306921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---