Simulation Results: uart

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.56 %
  • code
  • 92.55 %
  • assert
  • 97.12 %
  • func
  • 52.02 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.90 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.980s 253.254us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.710s 14.584us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.600s 20.850us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.060s 4339.449us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.820s 141.187us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.750s 75.500us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.600s 20.850us 1 1 100.00
uart_csr_aliasing 0.820s 141.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 6.480s 34191.743us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.980s 253.254us 1 1 100.00
uart_tx_rx 6.480s 34191.743us 1 1 100.00
parity_error 2 2 100.00
uart_intr 15.300s 127034.023us 1 1 100.00
uart_rx_parity_err 163.450s 189485.842us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 6.480s 34191.743us 1 1 100.00
uart_intr 15.300s 127034.023us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 41.930s 100393.381us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 18.570s 40798.221us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 10.400s 14150.695us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 15.300s 127034.023us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 15.300s 127034.023us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 15.300s 127034.023us 1 1 100.00
perf 1 1 100.00
uart_perf 110.280s 4593.465us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.700s 6931.759us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.700s 6931.759us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 1.910s 4084.257us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 4.280s 4765.512us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 6.830s 6842.193us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.260s 2404.216us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 222.740s 169210.195us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 61.350s 46067.523us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.650s 22.093us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.780s 32.993us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.630s 41.583us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.630s 41.583us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.710s 14.584us 1 1 100.00
uart_csr_rw 0.600s 20.850us 1 1 100.00
uart_csr_aliasing 0.820s 141.187us 1 1 100.00
uart_same_csr_outstanding 0.930s 40.736us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.710s 14.584us 1 1 100.00
uart_csr_rw 0.600s 20.850us 1 1 100.00
uart_csr_aliasing 0.820s 141.187us 1 1 100.00
uart_same_csr_outstanding 0.930s 40.736us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.990s 74.336us 1 1 100.00
uart_tl_intg_err 1.200s 366.090us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.200s 366.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 17.890s 2462.696us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 72666883044921755407705462470870082633080499397860571893582033627768608411336 74
UVM_ERROR @ 591228894 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 591617786 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 591728898 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 592062234 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata