Simulation Results: adc_ctrl

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.69 %
  • code
  • 92.22 %
  • assert
  • 91.90 %
  • func
  • 12.94 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 85.94 %
  • toggle
  • 99.76 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.390s 5794.404us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.600s 1325.549us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.780s 519.261us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 85.750s 49748.553us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.940s 1116.013us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.940s 544.806us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.780s 519.261us 1 1 100.00
adc_ctrl_csr_aliasing 1.940s 1116.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.700s 454.382us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.790s 374.023us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.730s 473.883us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.210s 399.558us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.620s 305.550us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 1.070s 384.310us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.770s 409.769us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.740s 354.591us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.750s 5488.822us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 11.440s 33875.146us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 48.570s 118097.552us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.590s 724.800us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.740s 475.485us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.760s 396.813us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.090s 481.600us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.090s 481.600us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.600s 1325.549us 1 1 100.00
adc_ctrl_csr_rw 0.780s 519.261us 1 1 100.00
adc_ctrl_csr_aliasing 1.940s 1116.013us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.450s 2381.011us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.600s 1325.549us 1 1 100.00
adc_ctrl_csr_rw 0.780s 519.261us 1 1 100.00
adc_ctrl_csr_aliasing 1.940s 1116.013us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.450s 2381.011us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 5.210s 4242.320us 1 1 100.00
adc_ctrl_tl_intg_err 6.950s 4437.753us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.950s 4437.753us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 1.710s 757.148us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 51128769137833265779911988348827986983674443691169162791304223066288680071197 386
UVM_INFO @ 454381780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 53486137065464875765306909913469185329491075770620291126216664445707713542703 386
UVM_INFO @ 374022927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 37054340046696923932255920141284414959593228663937834853406462753102505028029 386
UVM_INFO @ 473882989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 56233063980717507659425174367433330794189125124515688836733081535540528926291 386
UVM_INFO @ 399557863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 86255125260633643234661840138685781750138843536121354198279773517397757592859 386
UVM_INFO @ 305550232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 34257441266271556736192385946591495212302140526529771357152572480150026242574 386
UVM_INFO @ 384309518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 5010056277366218923388695629392528406475169839200576268128879042389287328688 386
UVM_INFO @ 354590939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 80252210177439109588525367524302973086219716187111066554184918132353417691375 386
UVM_INFO @ 409768608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 108271079851680087476787173573920263141196741317422355667128097614476530164993 399
UVM_INFO @ 757148422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 29615417320876850165559454885651603308742968097783874607297885737415411090526 387
UVM_INFO @ 724799866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---