Simulation Results: aes/unmasked

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.20 %
  • code
  • 90.39 %
  • assert
  • 97.73 %
  • func
  • 76.48 %
  • block
  • 90.74 %
  • line
  • 92.27 %
  • branch
  • 82.42 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 109.829us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 99.246us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 79.905us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 86.988us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 154.600us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 268.456us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 61.253us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 86.988us 1 1 100.00
aes_csr_aliasing 2.000s 268.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 99.246us 1 1 100.00
aes_config_error 2.000s 67.042us 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 99.246us 1 1 100.00
aes_config_error 2.000s 67.042us 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 62.902us 1 1 100.00
aes_b2b 4.000s 93.977us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 1.000s 99.246us 1 1 100.00
aes_config_error 2.000s 67.042us 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
aes_alert_reset 2.000s 136.428us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 81.595us 1 1 100.00
aes_config_error 2.000s 67.042us 1 1 100.00
aes_alert_reset 2.000s 136.428us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 548.234us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 136.540us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 136.428us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 62.902us 1 1 100.00
aes_sideload 2.000s 390.118us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 134.092us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 15.000s 1261.324us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 56.637us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 186.818us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 186.818us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 79.905us 1 1 100.00
aes_csr_rw 2.000s 86.988us 1 1 100.00
aes_csr_aliasing 2.000s 268.456us 1 1 100.00
aes_same_csr_outstanding 2.000s 149.595us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 79.905us 1 1 100.00
aes_csr_rw 2.000s 86.988us 1 1 100.00
aes_csr_aliasing 2.000s 268.456us 1 1 100.00
aes_same_csr_outstanding 2.000s 149.595us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 407.464us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 2.000s 109.084us 0 1 0.00
aes_control_fi 1.000s 65.527us 1 1 100.00
aes_cipher_fi 2.000s 58.481us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 120.144us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 120.144us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 120.144us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 120.144us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 126.149us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1506.761us 1 1 100.00
aes_tl_intg_err 2.000s 307.580us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 307.580us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 136.428us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 120.144us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 120.144us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 1.000s 99.246us 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
aes_alert_reset 2.000s 136.428us 1 1 100.00
aes_core_fi 2.000s 100.183us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 67.042us 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
aes_core_fi 2.000s 100.183us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 120.144us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 62.502us 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 62.902us 1 1 100.00
aes_sideload 2.000s 390.118us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 62.502us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 62.502us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 62.502us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 62.502us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 62.502us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 62.902us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 109.084us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 109.084us 0 1 0.00
aes_control_fi 1.000s 65.527us 1 1 100.00
aes_cipher_fi 2.000s 58.481us 1 1 100.00
aes_ctr_fi 2.000s 50.979us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 109.084us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 109.084us 0 1 0.00
aes_control_fi 1.000s 65.527us 1 1 100.00
aes_cipher_fi 2.000s 58.481us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 58.481us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 109.084us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 109.084us 0 1 0.00
aes_control_fi 1.000s 65.527us 1 1 100.00
aes_ctr_fi 2.000s 50.979us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 109.084us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 109.084us 0 1 0.00
aes_control_fi 1.000s 65.527us 1 1 100.00
aes_cipher_fi 2.000s 58.481us 1 1 100.00
aes_ctr_fi 2.000s 50.979us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 136.428us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 109.084us 0 1 0.00
aes_control_fi 1.000s 65.527us 1 1 100.00
aes_cipher_fi 2.000s 58.481us 1 1 100.00
aes_ctr_fi 2.000s 50.979us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 109.084us 0 1 0.00
aes_control_fi 1.000s 65.527us 1 1 100.00
aes_cipher_fi 2.000s 58.481us 1 1 100.00
aes_ctr_fi 2.000s 50.979us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 109.084us 0 1 0.00
aes_control_fi 1.000s 65.527us 1 1 100.00
aes_ctr_fi 2.000s 50.979us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 109.084us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 109.084us 0 1 0.00
aes_control_fi 1.000s 65.527us 1 1 100.00
aes_cipher_fi 2.000s 58.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 719.923us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 55904740808005653308373642525548571519910111869574867490680892596518376777088 4340
UVM_INFO @ 407463558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 3897091724253430187128952391168855197386671754044387724519232315475454371960 244
UVM_INFO @ 719923175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 95102824857536879252391257108283714028243909189547949446229959796337760089764 3417
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0