| V1 |
|
100.00% |
| V2 |
|
89.47% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 44.480s | 2498.258us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.030s | 66.653us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_csr_rw | 6.920s | 786.637us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 177.790s | 10625.815us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 78.440s | 2167.716us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 6.720s | 548.574us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| alert_handler_csr_rw | 6.920s | 786.637us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 78.440s | 2167.716us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 1 | 1 | 100.00 | |||
| alert_handler_esc_alert_accum | 13.130s | 252.129us | 1 | 1 | 100.00 | |
| esc_timeout | 1 | 1 | 100.00 | |||
| alert_handler_esc_intr_timeout | 24.190s | 2115.924us | 1 | 1 | 100.00 | |
| entropy | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 749.540s | 13775.588us | 1 | 1 | 100.00 | |
| sig_int_fail | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 36.370s | 11410.420us | 1 | 1 | 100.00 | |
| clk_skew | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 44.480s | 2498.258us | 1 | 1 | 100.00 | |
| random_alerts | 1 | 1 | 100.00 | |||
| alert_handler_random_alerts | 31.410s | 3237.093us | 1 | 1 | 100.00 | |
| random_classes | 1 | 1 | 100.00 | |||
| alert_handler_random_classes | 24.300s | 456.641us | 1 | 1 | 100.00 | |
| ping_timeout | 0 | 1 | 0.00 | |||
| alert_handler_ping_timeout | 11.620s | 407.300us | 0 | 1 | 0.00 | |
| lpg | 2 | 2 | 100.00 | |||
| alert_handler_lpg | 1034.430s | 67569.433us | 1 | 1 | 100.00 | |
| alert_handler_lpg_stub_clk | 1388.880s | 38417.058us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| alert_handler_stress_all | 1887.740s | 61285.285us | 1 | 1 | 100.00 | |
| alert_handler_entropy_stress_test | 0 | 1 | 0.00 | |||
| alert_handler_entropy_stress | 5.100s | 122.467us | 0 | 1 | 0.00 | |
| alert_handler_alert_accum_saturation | 1 | 1 | 100.00 | |||
| alert_handler_alert_accum_saturation | 2.220s | 20.707us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| alert_handler_intr_test | 1.230s | 8.637us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 6.640s | 648.955us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 6.640s | 648.955us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.030s | 66.653us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 6.920s | 786.637us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 78.440s | 2167.716us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 15.320s | 316.060us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 4.030s | 66.653us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 6.920s | 786.637us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 78.440s | 2167.716us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 15.320s | 316.060us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 258.650s | 23532.388us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 258.650s | 23532.388us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 258.650s | 23532.388us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 258.650s | 23532.388us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 750.620s | 29639.116us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| alert_handler_tl_intg_err | 58.340s | 5229.977us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| alert_handler_tl_intg_err | 58.340s | 5229.977us | 1 | 1 | 100.00 | |
| sec_cm_config_shadow | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 258.650s | 23532.388us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 44.480s | 2498.258us | 1 | 1 | 100.00 | |
| sec_cm_alert_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 44.480s | 2498.258us | 1 | 1 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 44.480s | 2498.258us | 1 | 1 | 100.00 | |
| sec_cm_class_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 44.480s | 2498.258us | 1 | 1 | 100.00 | |
| sec_cm_alert_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 36.370s | 11410.420us | 1 | 1 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 1 | 1 | 100.00 | |||
| alert_handler_lpg | 1034.430s | 67569.433us | 1 | 1 | 100.00 | |
| sec_cm_esc_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 36.370s | 11410.420us | 1 | 1 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 749.540s | 13775.588us | 1 | 1 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 749.540s | 13775.588us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| sec_cm_accu_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 10.360s | 475.119us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_stress_all_with_rand_reset | 85.160s | 7000.052us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 1 test run | |||
| alert_handler_ping_timeout | 38634976679714949134882003687662997145353623631838309996028903985076874234773 | 80 |
UVM_INFO @ 407300288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 1 test run | |||
| alert_handler_entropy_stress | 101424708327922732289416755476881250683107200584289256044591335659120950170018 | 172 |
UVM_INFO @ 122466582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|