Simulation Results: chip

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.70 %
  • code
  • 81.72 %
  • assert
  • 97.37 %
  • func
  • 57.01 %
  • line
  • 94.41 %
  • branch
  • 94.14 %
  • cond
  • 89.79 %
  • toggle
  • 73.10 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
88.45%
V2S
100.00%
V3
65.38%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 173.540s 3133.392us 1 1 100.00
chip_sw_example_rom 95.500s 2788.612us 1 1 100.00
chip_sw_example_manufacturer 193.450s 3313.422us 1 1 100.00
chip_sw_example_concurrency 208.920s 3391.029us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 262.030s 6556.580us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 490.270s 5688.210us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 964.560s 12868.983us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3960.180s 29083.701us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 69.810s 2045.258us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3960.180s 29083.701us 1 1 100.00
chip_csr_rw 490.270s 5688.210us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 7.610s 186.050us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 405.090s 5569.811us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 405.090s 5569.811us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 405.090s 5569.811us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 439.330s 5049.771us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 439.330s 5049.771us 1 1 100.00
chip_sw_uart_tx_rx_idx1 413.490s 4893.617us 1 1 100.00
chip_sw_uart_tx_rx_idx2 482.210s 4949.058us 1 1 100.00
chip_sw_uart_tx_rx_idx3 389.900s 4850.894us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1981.610s 13630.097us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1287.860s 9401.226us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1159.700s 13683.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 257.400s 5681.937us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 257.400s 5681.937us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 219.780s 2817.366us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 468.560s 7461.006us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 179.200s 3550.040us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 494.830s 7312.200us 1 1 100.00
chip_tap_straps_testunlock0 486.800s 7994.724us 1 1 100.00
chip_tap_straps_rma 195.800s 3937.654us 1 1 100.00
chip_tap_straps_prod 120.360s 3094.044us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 528.940s 7944.135us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 528.940s 7944.135us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 806.520s 9813.734us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1118.830s 10966.630us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 444.800s 4886.508us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 600.830s 6558.813us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4364.750s 19274.340us 1 1 100.00
chip_sw_aes_enc_jitter_en 267.590s 3908.782us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 985.230s 9565.793us 1 1 100.00
chip_sw_hmac_enc_jitter_en 247.280s 3541.726us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1712.530s 14038.616us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 234.410s 3255.831us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 464.670s 5619.773us 1 1 100.00
chip_sw_clkmgr_jitter 228.870s 3578.276us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 227.180s 3810.295us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 431.290s 6948.944us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 292.860s 5929.663us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 211.310s 3868.842us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 292.860s 5929.663us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 177.620s 3239.682us 1 1 100.00
chip_sw_aes_smoketest 211.160s 3517.892us 1 1 100.00
chip_sw_aon_timer_smoketest 253.120s 3834.087us 1 1 100.00
chip_sw_clkmgr_smoketest 157.640s 3601.670us 1 1 100.00
chip_sw_csrng_smoketest 146.160s 3653.280us 1 1 100.00
chip_sw_entropy_src_smoketest 1263.390s 8139.468us 1 1 100.00
chip_sw_gpio_smoketest 229.130s 4165.573us 1 1 100.00
chip_sw_hmac_smoketest 244.920s 3958.804us 1 1 100.00
chip_sw_kmac_smoketest 253.120s 4192.587us 1 1 100.00
chip_sw_otbn_smoketest 1475.200s 10456.159us 1 1 100.00
chip_sw_pwrmgr_smoketest 336.660s 6621.502us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 348.010s 7381.565us 1 1 100.00
chip_sw_rv_plic_smoketest 161.040s 3145.180us 1 1 100.00
chip_sw_rv_timer_smoketest 163.050s 3162.741us 1 1 100.00
chip_sw_rstmgr_smoketest 175.060s 3035.839us 1 1 100.00
chip_sw_sram_ctrl_smoketest 249.180s 3372.970us 1 1 100.00
chip_sw_uart_smoketest 202.620s 4370.795us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 213.260s 4327.310us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 462.410s 6378.467us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 9962.710s 60390.079us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3360.060s 15637.186us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 225.590s 6616.053us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 1145.900s 14909.015us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 1097.030s 15973.959us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7614.700s 54391.719us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 9441.950s 55935.674us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 78.500s 2344.298us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 78.500s 2344.298us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3960.180s 29083.701us 1 1 100.00
chip_same_csr_outstanding 2677.310s 26107.557us 1 1 100.00
chip_csr_hw_reset 262.030s 6556.580us 1 1 100.00
chip_csr_rw 490.270s 5688.210us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3960.180s 29083.701us 1 1 100.00
chip_same_csr_outstanding 2677.310s 26107.557us 1 1 100.00
chip_csr_hw_reset 262.030s 6556.580us 1 1 100.00
chip_csr_rw 490.270s 5688.210us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 58.490s 2158.454us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.300s 36.611us 1 1 100.00
xbar_smoke_large_delays 40.810s 6452.606us 1 1 100.00
xbar_smoke_slow_rsp 45.210s 3776.431us 1 1 100.00
xbar_random_zero_delays 22.700s 354.766us 1 1 100.00
xbar_random_large_delays 301.690s 48592.831us 1 1 100.00
xbar_random_slow_rsp 154.430s 15806.804us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 44.820s 1217.888us 1 1 100.00
xbar_error_and_unmapped_addr 33.430s 1118.655us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 29.940s 493.822us 1 1 100.00
xbar_error_and_unmapped_addr 33.430s 1118.655us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 84.440s 3506.634us 1 1 100.00
xbar_access_same_device_slow_rsp 623.140s 69143.676us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 27.160s 413.720us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 272.000s 10250.791us 1 1 100.00
xbar_stress_all_with_error 202.840s 4347.291us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 232.420s 1936.599us 1 1 100.00
xbar_stress_all_with_reset_error 94.240s 664.435us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3360.060s 15637.186us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 3185.910s 31190.125us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3256.990s 15911.974us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2692.310s 11658.457us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3372.670s 17677.503us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3434.700s 16111.892us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3650.210s 17994.877us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3459.980s 14911.843us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2718.730s 11502.029us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3276.860s 16091.462us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3581.320s 18008.872us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3584.140s 16281.380us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3336.580s 17564.817us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4963.950s 17897.158us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 6187.590s 24941.972us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 6289.860s 24010.547us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6185.210s 26765.629us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 6239.590s 25148.477us 1 1 100.00
rom_e2e_sigverify_always 14 15 93.33
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4905.830s 18561.808us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 6194.510s 24004.835us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 6091.950s 24378.778us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 209.010s 6164.899us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 5787.960s 23036.508us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2596.470s 12236.703us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3373.230s 16036.934us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3358.050s 15763.172us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3401.670s 15023.499us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3229.510s 14986.040us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2767.010s 15955.984us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3323.320s 16186.971us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3384.360s 15600.363us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3511.720s 15726.435us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3332.610s 15399.356us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2768.750s 14897.130us 1 1 100.00
rom_e2e_asm_init_dev 3446.820s 16472.409us 1 1 100.00
rom_e2e_asm_init_prod 3510.460s 16082.014us 1 1 100.00
rom_e2e_asm_init_prod_end 3533.260s 15752.613us 1 1 100.00
rom_e2e_asm_init_rma 3361.120s 15945.853us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 6722.680s 30442.787us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 7094.080s 30727.531us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3713.630s 19527.756us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3782.800s 17388.143us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.161s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.161s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 214.050s 3358.388us 1 1 100.00
chip_sw_aes_enc_jitter_en 267.590s 3908.782us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 192.090s 2861.225us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 138.350s 3145.258us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1454.910s 10552.163us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 211.890s 3330.872us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 454.400s 5556.849us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 473.510s 6228.990us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 504.570s 5582.999us 1 1 100.00
chip_plic_all_irqs_10 307.320s 4191.567us 1 1 100.00
chip_plic_all_irqs_20 393.730s 4854.699us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 255.190s 4316.518us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1573.860s 14445.312us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 387.420s 5409.835us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 177.470s 3666.132us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.141s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 814.430s 6402.213us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1203.500s 8947.353us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 950.410s 8752.257us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 11390.090s 257486.458us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 302.810s 4877.392us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 336.660s 6621.502us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 302.810s 4877.392us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 593.510s 9460.218us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 593.510s 9460.218us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 340.150s 8972.613us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 479.500s 6960.514us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 673.910s 6592.817us 1 1 100.00
chip_sw_aes_idle 138.350s 3145.258us 1 1 100.00
chip_sw_hmac_enc_idle 228.350s 3829.339us 1 1 100.00
chip_sw_kmac_idle 181.440s 2727.869us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 395.890s 6775.748us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 385.400s 5944.912us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 357.490s 6077.560us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 434.470s 6135.956us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 887.200s 12936.391us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 450.730s 5384.982us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 421.920s 5324.297us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 441.130s 4823.661us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 421.070s 5252.242us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 507.830s 5174.685us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 422.600s 5535.296us 1 1 100.00
chip_sw_ast_clk_outputs 806.520s 9813.734us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 807.710s 14020.666us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 441.130s 4823.661us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 421.070s 5252.242us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 444.800s 4886.508us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 600.830s 6558.813us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4364.750s 19274.340us 1 1 100.00
chip_sw_aes_enc_jitter_en 267.590s 3908.782us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 985.230s 9565.793us 1 1 100.00
chip_sw_hmac_enc_jitter_en 247.280s 3541.726us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1712.530s 14038.616us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 234.410s 3255.831us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 464.670s 5619.773us 1 1 100.00
chip_sw_clkmgr_jitter 228.870s 3578.276us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 199.510s 3579.474us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 415.740s 4821.300us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 696.730s 7340.567us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4300.960s 25668.558us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 225.540s 4116.225us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 218.100s 3859.589us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 691.490s 8026.335us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 208.490s 3528.449us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 405.590s 6982.124us 1 1 100.00
chip_sw_flash_init_reduced_freq 1351.660s 21997.874us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 13665.610s 134554.810us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 806.520s 9813.734us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 435.820s 4876.451us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 346.790s 4473.829us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 473.510s 6228.990us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 814.430s 6402.213us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 2359.950s 25144.001us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 265.870s 4065.240us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 549.840s 7455.021us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 216.910s 3635.643us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 5186.690s 25207.982us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 184.840s 4187.754us 1 1 100.00
chip_sw_edn_entropy_reqs 814.990s 6783.671us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 184.840s 4187.754us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 2359.950s 25144.001us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 219.560s 3563.158us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1395.670s 20598.432us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 652.820s 5491.030us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 600.830s 6558.813us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 367.610s 4130.389us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 444.800s 4886.508us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 4402.360s 44775.329us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1395.670s 20598.432us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 264.310s 4204.259us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1830.250s 11600.754us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.720s 4106.487us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 4402.360s 44775.329us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.720s 4106.487us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.720s 4106.487us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.720s 4106.487us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 184.720s 4106.487us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 473.510s 6228.990us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 474.450s 16032.903us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 589.290s 5311.921us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 404.000s 6366.592us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 404.000s 6366.592us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 236.220s 4074.696us 1 1 100.00
chip_sw_hmac_enc_jitter_en 247.280s 3541.726us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 228.350s 3829.339us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 990.970s 7772.062us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1905.030s 12018.614us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 430.240s 4502.714us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 477.100s 5117.711us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 493.450s 5306.052us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 381.790s 4630.932us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1830.250s 11600.754us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1712.530s 14038.616us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1928.540s 13828.851us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1454.910s 10552.163us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4174.960s 20018.640us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 185.790s 3107.771us 1 1 100.00
chip_sw_kmac_mode_kmac 201.960s 3377.075us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 234.410s 3255.831us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1830.250s 11600.754us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 459.190s 8214.604us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 225.900s 3443.910us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1137.050s 7748.581us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 181.440s 2727.869us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 454.400s 5556.849us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 494.830s 7312.200us 1 1 100.00
chip_tap_straps_rma 195.800s 3937.654us 1 1 100.00
chip_tap_straps_prod 120.360s 3094.044us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 183.640s 3891.551us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 459.190s 8214.604us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 459.190s 8214.604us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 459.190s 8214.604us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 969.610s 8850.518us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 184.720s 4106.487us 0 1 0.00
chip_sw_flash_rma_unlocked 4402.360s 44775.329us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 257.780s 3434.777us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 612.590s 6316.199us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 606.470s 8710.051us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 585.860s 8085.487us 0 1 0.00
chip_sw_lc_ctrl_transition 459.190s 8214.604us 1 1 100.00
chip_sw_keymgr_key_derivation 1830.250s 11600.754us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 405.930s 9459.816us 1 1 100.00
chip_sw_sram_ctrl_execution_main 666.640s 9936.584us 1 1 100.00
chip_prim_tl_access 474.450s 16032.903us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 807.710s 14020.666us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 450.730s 5384.982us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 421.920s 5324.297us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 441.130s 4823.661us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 421.070s 5252.242us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 507.830s 5174.685us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 422.600s 5535.296us 1 1 100.00
chip_tap_straps_dev 494.830s 7312.200us 1 1 100.00
chip_tap_straps_rma 195.800s 3937.654us 1 1 100.00
chip_tap_straps_prod 120.360s 3094.044us 1 1 100.00
chip_rv_dm_lc_disabled 64.490s 3128.256us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 187.980s 4266.793us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 130.800s 3544.344us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 91.470s 3189.833us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 205.860s 4299.441us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 2051.640s 34119.375us 1 1 100.00
chip_rv_dm_lc_disabled 64.490s 3128.256us 0 1 0.00
chip_sw_lc_walkthrough 1 5 20.00
chip_sw_lc_walkthrough_dev 1033.100s 16033.983us 0 1 0.00
chip_sw_lc_walkthrough_prod 761.430s 13038.587us 0 1 0.00
chip_sw_lc_walkthrough_prodend 971.500s 27195.226us 0 1 0.00
chip_sw_lc_walkthrough_rma 536.180s 8190.890us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 2051.640s 34119.375us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 83.420s 2842.741us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 1111.590s 26132.020us 0 1 0.00
rom_volatile_raw_unlock 77.640s 3093.698us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4223.910s 17784.114us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4364.750s 19274.340us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 673.910s 6592.817us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 673.910s 6592.817us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 673.910s 6592.817us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 376.370s 4054.354us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 459.190s 8214.604us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1395.670s 20598.432us 1 1 100.00
chip_sw_otbn_mem_scramble 376.370s 4054.354us 1 1 100.00
chip_sw_keymgr_key_derivation 1830.250s 11600.754us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 520.980s 6094.968us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 231.420s 3358.868us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1395.670s 20598.432us 1 1 100.00
chip_sw_otbn_mem_scramble 376.370s 4054.354us 1 1 100.00
chip_sw_keymgr_key_derivation 1830.250s 11600.754us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 520.980s 6094.968us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 231.420s 3358.868us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 459.190s 8214.604us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 389.860s 4976.615us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 183.640s 3891.551us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 257.780s 3434.777us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 612.590s 6316.199us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 606.470s 8710.051us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 585.860s 8085.487us 0 1 0.00
chip_sw_lc_ctrl_transition 459.190s 8214.604us 1 1 100.00
chip_prim_tl_access 474.450s 16032.903us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 474.450s 16032.903us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1060.330s 9506.273us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 77.450s 2855.685us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1292.180s 29205.680us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 224.180s 7562.475us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 463.590s 9288.097us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 497.180s 8154.068us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1203.210s 26337.938us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 277.470s 5974.750us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 593.510s 9460.218us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1121.700s 15242.830us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 482.200s 5233.527us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 77.450s 2855.685us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 284.150s 4215.686us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1180.770s 13672.960us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 480.870s 7489.374us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 221.300s 4149.177us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 221.380s 6114.712us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 745.810s 9102.757us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1234.930s 15261.922us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2331.230s 38308.280us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 184.230s 3743.954us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 473.510s 6228.990us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 405.930s 9459.816us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 405.930s 9459.816us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1234.930s 15261.922us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 221.380s 6114.712us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 482.200s 5233.527us 1 1 100.00
chip_sw_pwrmgr_smoketest 336.660s 6621.502us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 381.310s 5664.319us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 461.370s 7355.433us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 275.140s 4370.810us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1573.860s 14445.312us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 160.500s 2746.455us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 473.510s 6228.990us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1203.500s 8947.353us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 542.470s 5448.081us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 557.780s 4534.175us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 195.500s 3191.091us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 231.420s 3358.868us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 461.370s 7355.433us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 461.370s 7355.433us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 151.320s 3700.984us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1396.310s 17595.234us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1325.890s 17070.920us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 381.310s 5664.319us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 228.270s 3400.058us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1532.690s 13451.794us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 195.800s 3937.654us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 64.490s 3128.256us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 504.570s 5582.999us 1 1 100.00
chip_plic_all_irqs_10 307.320s 4191.567us 1 1 100.00
chip_plic_all_irqs_20 393.730s 4854.699us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 188.340s 4038.439us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 227.340s 3685.521us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3360.060s 15637.186us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 258.100s 3538.786us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 237.210s 4161.534us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 247.940s 3825.360us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 256.820s 3771.008us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 520.980s 6094.968us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 464.670s 5619.773us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 592.860s 9626.216us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 458.870s 9287.609us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 666.640s 9936.584us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 473.510s 6228.990us 1 1 100.00
chip_sw_data_integrity_escalation 528.940s 7944.135us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 745.810s 9102.757us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1228.460s 24443.703us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 167.610s 3180.339us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 301.220s 4738.316us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 411.390s 5433.732us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1228.460s 24443.703us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1228.460s 24443.703us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 304.050s 5010.140us 0 1 0.00
chip_sw_sysrst_ctrl_flash_wp_l 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 304.050s 5010.140us 0 1 0.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 403.430s 7336.173us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.161s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 164.280s 3306.971us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 230.390s 3947.773us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 295.260s 3740.404us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 362.200s 4279.254us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1123.360s 9151.440us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6332.240s 32392.949us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1980.260s 12959.066us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 240.260s 3169.245us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 234.770s 3702.122us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 179.510s 3519.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 12188.380s 68618.246us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1335.090s 7116.784us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 207.240s 5251.556us 0 1 0.00
rom_e2e_jtag_debug_dev 235.690s 5696.771us 0 1 0.00
rom_e2e_jtag_debug_rma 558.200s 7583.925us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 107.700s 3167.784us 0 1 0.00
rom_e2e_jtag_inject_dev 268.050s 6219.835us 0 1 0.00
rom_e2e_jtag_inject_rma 113.620s 3568.028us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 189.095s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 316.200s 3790.364us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 378.510s 3728.715us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 1366.380s 7736.198us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1005.770s 7706.240us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 286.290s 2506.189us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 691.120s 6592.431us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 65.290s 2234.741us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 210.170s 3480.095us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 297.460s 6775.611us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 430.210s 5221.768us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1234.930s 15261.922us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 207.240s 5251.556us 0 1 0.00
rom_e2e_jtag_debug_dev 235.690s 5696.771us 0 1 0.00
rom_e2e_jtag_debug_rma 558.200s 7583.925us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 497.720s 6060.917us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 473.510s 6228.990us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 6037.360s 39336.990us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 6037.360s 39336.990us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 250.720s 4860.920us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 439.330s 5049.771us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3530.590s 19999.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 246.260s 3551.209us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 19.310s 10.360us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 7.360s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 180.070s 3101.946us 1 1 100.00
chip_sw_otp_ctrl_descrambling 242.500s 2988.864us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 262.100s 3831.494us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 10.223s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 247.390s 3395.404us 1 1 100.00
ate_bootstrap_flash_erase 733.840s 10010.360us 0 1 0.00
ate_bootstrap_one_frame 7166.450s 44017.990us 1 1 100.00
ate_bootstrap_disjoint 10258.810s 79117.423us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 41816731529096811302196749532941323520646050446151476344503193853317552935105 323
UVM_ERROR @ 6114.712500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6114.712500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 83108131623859886821623578634588519917020420277246409588572847629058572402032 322
UVM_ERROR @ 5974.750000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5974.750000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 96685075236098617121877572467095038808772303463344951347946022295021751638378 328
UVM_ERROR @ 9288.097000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9288.097000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 3599184815486494438363712801610460048970486042555518603624422448039411653495 364
UVM_ERROR @ 13672.960000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 13672.960000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 65858344587960563023284218539931433463311634002148211713822753585507315542907 322
UVM_ERROR @ 9460.217500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9460.217500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 5 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 112815209188408654606496305107585718368944452673819783510435709009616886861385 330
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 110351921402732970358373880375968045405795801037738800391328042921739077538486 355
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 66326886639541320912088040438306165958794251735268270478887631135537788577357 310
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 63212643976403558830574633263061412107395867315063054160772111441538392105244 313
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 114478446769921369565376079795280521889941842560953031366463164180959452989114 306
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 36477995908044614376707571280050389339362087715530790085364717300149039359965 372
UVM_INFO @ 16033.982968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 76949887006283963501194018624852276524581447115857962512016587872607713418981 372
UVM_INFO @ 13038.586580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 101641428027664001088655888670429146478742182055743789703889458992586224432109 344
UVM_INFO @ 8190.890000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 109882015295562356213760012670465977135775635947840533114724792101052224277988 None
chip_sw_alert_handler_lpg_sleep_mode_pings 71641909825909437154545140362118640167873694193312128304997477250169037777197 None
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 5548617260320465920485910074264673329032815506390601560789976574326159027765 356
UVM_INFO @ 12018.613717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 99075056915526873303752487612553426369574449313990614060230619014283667981923 337
UVM_INFO @ 20018.640133 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 98640109676436132392392622858095488330689035184687671853036440701420757959384 220
TL item was: req: (cip_tl_seq_item@44180) { a_addr: 'h107c8 a_data: 'h222a6be1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h37 a_opcode: 'h4 a_user: 'h19570 d_param: 'h0 d_source: 'h37 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2344.297793 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 111493576952392904325357510149449251616056977360619140268286755147502282588899 227
TL item was: req: (cip_tl_seq_item@31924) { a_addr: 'h10370 a_data: 'hf9bcf83c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h22 a_opcode: 'h4 a_user: 'h19e62 d_param: 'h0 d_source: 'h22 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2045.258224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 63884107740762413133637495213338856978777954345129118788119002474787441854783 None
---- STDERR ----
Another command (pid=2293603) is running. Waiting for it to complete on the server (server_pid=266687)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 104943019920384992194876752441057490213691227788524985399197472731662743727159 None
Another command (pid=725209) is running. Waiting for it to complete on the server (server_pid=266687)...
Another command (pid=720349) is running. Waiting for it to complete on the server (server_pid=266687)...
Another command (pid=697860) is running. Waiting for it to complete on the server (server_pid=266687)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 28191578469517022155466217709756406842791658376799530091011825112349317039423 304
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 25203649933306860614033174904888740394348644016791379071216357505896583790421 330
UVM_INFO @ 4161.534120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 91691038751298827166223424053790525534038419300327333230804051421160878757164 312
UVM_INFO @ 4106.487000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 3429346632182276372545663896918284369139737006645102930200088562527064745429 345
UVM_INFO @ 8085.486951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 50346763220819661599074195390823501813524137298815565186312468639977084171279 319
UVM_ERROR @ 3480.095286 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3480.095286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 54352963468390012356783789977720192015611116360636166014366364348424829541302 285
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_prodend 49494995907727237283979271307185934904753680628040488144215922518366252496475 311
UVM_INFO @ 27195.225575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_volatile_raw_unlock_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 26291237954897505241037654479907087477524516099101093010025563104568148741858 317
UVM_INFO @ 26132.019727 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 46800840669318306641422272317398642783226318372363806965939076840130194552089 306
UVM_ERROR @ 2855.684550 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2855.684550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 1 test run
chip_sw_pwrmgr_sleep_power_glitch_reset 73278668502499439040173614452246812388834375563679489837256500068371670982191 316
UVM_ERROR @ 4149.176656 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 4149.176656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_sysrst_ctrl_ec_rst_l_vseq.sv:138) [chip_sw_sysrst_ctrl_ec_rst_l_vseq] Timed out waiting for ec_rst to go high. 1 test run
chip_sw_sysrst_ctrl_ec_rst_l 17757724858153085162340822858749723237893778081686166175273226550190743946031 314
UVM_INFO @ 5010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:351)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 40079322722638824551611639737228660347514820895793879167817003428524519333828 310
UVM_INFO @ 3330.872262 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 10371043886274349618229357325779977113561253151561525062065729836477550688063 311
UVM_INFO @ 3666.132086 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 9370602558504130803870075352932514717773246996050853783295682443942618701718 346
UVM_INFO @ 3790.363881 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 101834377680462463033644044243836609147754751817336238785951940435496600174344 332
UVM_INFO @ 13451.793890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 28217143555592213654899582488353980000582299097185543768783580402871099829569 218
UVM_INFO @ 3128.256083 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 14278840760149154874314949112457148808512754127309543661136253689449462949111 321
UVM_INFO @ 14909.014532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 107642017286264631044391942497750429059365321244386783683391090904826696252833 332
UVM_INFO @ 15973.958990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 76807115056687592810542064594377499549550247601830035483480307305765796409016 330
UVM_INFO @ 10966.630426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 38558956406925881064086933992433613383629733194631991502694756662567943131411 275
UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' 1 test run
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 28378616971166705923285139752652638850233842890824906444621816591856185162077 368
UVM_ERROR @ 6164.899160 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 6164.899160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*]) 1 test run
rom_e2e_jtag_debug_test_unlocked0 61304390016892099370679551464923833373940459636128749451843452686058804474430 320
UVM_INFO @ 5251.556404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds 1 test run
rom_e2e_jtag_debug_dev 59070936333083607680790802919915965249757143248613218637566156656275619585365 321
UVM_INFO @ 5696.771445 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 20961701816571747126948819619241778883089515119197294187958115571300430860433 322
UVM_INFO @ 19527.755535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 38875295338201733016590966049638034475479664215114347133265555956012341428739 330
UVM_ERROR @ 6378.466604 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6378.466604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---