Simulation Results: clkmgr

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.43 %
  • code
  • 97.92 %
  • assert
  • 94.63 %
  • func
  • 84.73 %
  • line
  • 98.93 %
  • branch
  • 98.64 %
  • cond
  • 92.82 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
83.33%
V2
92.86%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.800s 40.045us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.750s 48.171us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.790s 26.433us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.120s 289.579us 1 1 100.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 1.160s 80.446us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.430s 323.762us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.790s 26.433us 1 1 100.00
clkmgr_csr_aliasing 1.160s 80.446us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.860s 25.704us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.910s 96.257us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.810s 29.152us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.780s 15.767us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.800s 40.045us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 5.810s 1281.480us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.510s 2207.249us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 5.810s 1281.480us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 9.670s 2407.742us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.710s 14.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.540s 132.329us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.540s 132.329us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
clkmgr_csr_hw_reset 0.750s 48.171us 1 1 100.00
clkmgr_csr_rw 0.790s 26.433us 1 1 100.00
clkmgr_csr_aliasing 1.160s 80.446us 0 1 0.00
clkmgr_same_csr_outstanding 1.330s 179.681us 1 1 100.00
tl_d_partial_access 3 4 75.00
clkmgr_csr_hw_reset 0.750s 48.171us 1 1 100.00
clkmgr_csr_rw 0.790s 26.433us 1 1 100.00
clkmgr_csr_aliasing 1.160s 80.446us 0 1 0.00
clkmgr_same_csr_outstanding 1.330s 179.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.800s 19.515us 0 1 0.00
clkmgr_tl_intg_err 1.370s 141.659us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.330s 642.998us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.330s 642.998us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.330s 642.998us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.330s 642.998us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.910s 21.107us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.370s 141.659us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 5.810s 1281.480us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.510s 2207.249us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.330s 642.998us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.790s 51.940us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.150s 68.756us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.850s 30.660us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.870s 108.090us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.660s 22.487us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.790s 26.433us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.800s 19.515us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 26.433us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.790s 26.433us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.800s 19.515us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.700s 493.014us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 89.620s 20446.564us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 71474515216226753823103029676493990019295477461398973653029392058241365930750 75
UVM_INFO @ 21107046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 95323407226551624016820827791876648947575577859052221609371710474533560902833 95
UVM_INFO @ 19515212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.recov_err_code reset value: * 1 test run
clkmgr_csr_aliasing 97203364167478452458108690044909190014854776045430768556853754887146937055952 76
UVM_INFO @ 80445735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---