Simulation Results: edn/edn0

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.78 %
  • code
  • 84.62 %
  • assert
  • 96.96 %
  • func
  • 81.75 %
  • line
  • 97.99 %
  • branch
  • 93.72 %
  • cond
  • 89.03 %
  • toggle
  • 90.77 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.870s 59.303us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.910s 43.778us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.820s 37.665us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.130s 163.529us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.310s 66.479us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.650s 40.878us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.820s 37.665us 1 1 100.00
edn_csr_aliasing 1.310s 66.479us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.140s 71.720us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.140s 71.720us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.140s 71.720us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.030s 24.085us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.090s 117.884us 1 1 100.00
errs 1 1 100.00
edn_err 1.030s 44.269us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 35.662us 1 1 100.00
edn_disable_auto_req_mode 0.940s 44.839us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.400s 588.933us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 25.703us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.910s 17.313us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.280s 1503.153us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.280s 1503.153us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.910s 43.778us 1 1 100.00
edn_csr_rw 0.820s 37.665us 1 1 100.00
edn_csr_aliasing 1.310s 66.479us 1 1 100.00
edn_same_csr_outstanding 1.000s 49.543us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.910s 43.778us 1 1 100.00
edn_csr_rw 0.820s 37.665us 1 1 100.00
edn_csr_aliasing 1.310s 66.479us 1 1 100.00
edn_same_csr_outstanding 1.000s 49.543us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.930s 587.668us 1 1 100.00
edn_tl_intg_err 1.140s 80.065us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.020s 20.440us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.090s 117.884us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.930s 587.668us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.930s 587.668us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.930s 587.668us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.930s 587.668us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.090s 117.884us 1 1 100.00
edn_sec_cm 3.930s 587.668us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.090s 117.884us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.140s 80.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 101.210s 34283.231us 1 1 100.00