Simulation Results: edn/edn1

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.17 %
  • code
  • 81.54 %
  • assert
  • 97.14 %
  • func
  • 79.83 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 87.46 %
  • toggle
  • 86.52 %
  • FSM
  • 42.05 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 126.696us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 39.956us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.730s 52.441us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.440s 145.497us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.070s 23.527us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.590s 103.633us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.730s 52.441us 1 1 100.00
edn_csr_aliasing 1.070s 23.527us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.900s 94.216us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.900s 94.216us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.900s 94.216us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.830s 64.402us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.870s 22.971us 1 1 100.00
errs 1 1 100.00
edn_err 1.000s 29.033us 1 1 100.00
disable 1 2 50.00
edn_disable 0.820s 153.801us 1 1 100.00
edn_disable_auto_req_mode 3.470s 500.000us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.730s 372.540us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.860s 71.092us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.010s 21.189us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.390s 31.854us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.390s 31.854us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 39.956us 1 1 100.00
edn_csr_rw 0.730s 52.441us 1 1 100.00
edn_csr_aliasing 1.070s 23.527us 1 1 100.00
edn_same_csr_outstanding 0.860s 29.059us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 39.956us 1 1 100.00
edn_csr_rw 0.730s 52.441us 1 1 100.00
edn_csr_aliasing 1.070s 23.527us 1 1 100.00
edn_same_csr_outstanding 0.860s 29.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.350s 1111.481us 1 1 100.00
edn_tl_intg_err 1.500s 79.704us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 39.113us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.870s 22.971us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.350s 1111.481us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.350s 1111.481us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.350s 1111.481us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.350s 1111.481us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.870s 22.971us 1 1 100.00
edn_sec_cm 3.350s 1111.481us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.870s 22.971us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.500s 79.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 36.030s 2521.458us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 73074413676704920545285593173773256275672706607800602106918823837515481158251 251
UVM_INFO @ 2521457644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 77986993271759037384834641708003960472427146798424591943800557353620600648928 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---