| V1 |
|
100.00% |
| V2 |
|
94.12% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.010s | 137.930us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 0.870s | 172.859us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 0.980s | 24.223us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.030s | 213.394us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.670s | 20.614us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.910s | 24.252us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 2.150s | 326.825us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 0.880s | 94.151us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 0.890s | 116.991us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| gpio_csr_rw | 0.910s | 24.252us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.880s | 94.151us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 0.820s | 60.341us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 0.940s | 51.189us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.930s | 40.060us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 0.830s | 88.675us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 2.290s | 659.351us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 1.370s | 81.523us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 9.630s | 631.984us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 1.760s | 167.581us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 0.880s | 40.082us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 2.750s | 2823.277us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.710s | 17.496us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.740s | 17.717us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 0.980s | 23.161us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 0.980s | 23.161us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.910s | 24.252us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.780s | 34.377us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.880s | 94.151us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.670s | 20.614us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| gpio_csr_rw | 0.910s | 24.252us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.780s | 34.377us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 0.880s | 94.151us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 0.670s | 20.614us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 1.010s | 290.724us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 0.920s | 626.871us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 1.010s | 290.724us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.690s | 83.196us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 8.670s | 7392.864us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 1 test run | |||
| gpio_stress_all | 8714723884604942385487892982535938499452325055726250637982451515166318654022 | 76 |
UVM_INFO @ 2823276777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) | 1 test run | |||
| gpio_stress_all_with_rand_reset | 8553632856180523635958085354095997763629770975953805222799725800893571942325 | 310 |
UVM_INFO @ 7392864269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|