Simulation Results: hmac

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.99 %
  • code
  • 97.56 %
  • assert
  • 97.60 %
  • func
  • 41.81 %
  • line
  • 99.59 %
  • branch
  • 98.68 %
  • cond
  • 95.39 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.520s 1492.016us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.930s 23.738us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.170s 19.075us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.720s 308.010us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.700s 359.128us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 343.850s 160670.835us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.170s 19.075us 1 1 100.00
hmac_csr_aliasing 4.700s 359.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 61.530s 8609.304us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 47.690s 1650.353us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 237.020s 63684.840us 1 1 100.00
hmac_test_sha384_vectors 20.590s 609.658us 1 1 100.00
hmac_test_sha512_vectors 19.870s 601.221us 1 1 100.00
hmac_test_hmac256_vectors 7.240s 1094.151us 1 1 100.00
hmac_test_hmac384_vectors 6.470s 196.186us 1 1 100.00
hmac_test_hmac512_vectors 9.220s 1220.927us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 9.200s 2040.201us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 230.640s 9270.226us 1 1 100.00
error 1 1 100.00
hmac_error 81.090s 9332.065us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 97.700s 19366.219us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.520s 1492.016us 1 1 100.00
hmac_long_msg 61.530s 8609.304us 1 1 100.00
hmac_back_pressure 47.690s 1650.353us 1 1 100.00
hmac_datapath_stress 230.640s 9270.226us 1 1 100.00
hmac_burst_wr 9.200s 2040.201us 1 1 100.00
hmac_stress_all 4.310s 1426.874us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.520s 1492.016us 1 1 100.00
hmac_long_msg 61.530s 8609.304us 1 1 100.00
hmac_back_pressure 47.690s 1650.353us 1 1 100.00
hmac_datapath_stress 230.640s 9270.226us 1 1 100.00
hmac_wipe_secret 97.700s 19366.219us 1 1 100.00
hmac_test_sha256_vectors 237.020s 63684.840us 1 1 100.00
hmac_test_sha384_vectors 20.590s 609.658us 1 1 100.00
hmac_test_sha512_vectors 19.870s 601.221us 1 1 100.00
hmac_test_hmac256_vectors 7.240s 1094.151us 1 1 100.00
hmac_test_hmac384_vectors 6.470s 196.186us 1 1 100.00
hmac_test_hmac512_vectors 9.220s 1220.927us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.520s 1492.016us 1 1 100.00
hmac_long_msg 61.530s 8609.304us 1 1 100.00
hmac_back_pressure 47.690s 1650.353us 1 1 100.00
hmac_datapath_stress 230.640s 9270.226us 1 1 100.00
hmac_burst_wr 9.200s 2040.201us 1 1 100.00
hmac_error 81.090s 9332.065us 1 1 100.00
hmac_wipe_secret 97.700s 19366.219us 1 1 100.00
hmac_test_sha256_vectors 237.020s 63684.840us 1 1 100.00
hmac_test_sha384_vectors 20.590s 609.658us 1 1 100.00
hmac_test_sha512_vectors 19.870s 601.221us 1 1 100.00
hmac_test_hmac256_vectors 7.240s 1094.151us 1 1 100.00
hmac_test_hmac384_vectors 6.470s 196.186us 1 1 100.00
hmac_test_hmac512_vectors 9.220s 1220.927us 1 1 100.00
hmac_stress_all 4.310s 1426.874us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 4.310s 1426.874us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.740s 36.408us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.740s 10.906us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.290s 113.469us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.290s 113.469us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.930s 23.738us 1 1 100.00
hmac_csr_rw 1.170s 19.075us 1 1 100.00
hmac_csr_aliasing 4.700s 359.128us 1 1 100.00
hmac_same_csr_outstanding 2.650s 571.877us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.930s 23.738us 1 1 100.00
hmac_csr_rw 1.170s 19.075us 1 1 100.00
hmac_csr_aliasing 4.700s 359.128us 1 1 100.00
hmac_same_csr_outstanding 2.650s 571.877us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.130s 119.862us 1 1 100.00
hmac_tl_intg_err 2.210s 166.229us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.210s 166.229us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.520s 1492.016us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.790s 88.178us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 46.930s 15118.180us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.110s 42.729us 1 1 100.00