Simulation Results: i2c

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.37 %
  • code
  • 80.79 %
  • assert
  • 97.04 %
  • func
  • 81.29 %
  • line
  • 96.32 %
  • branch
  • 92.05 %
  • cond
  • 84.74 %
  • toggle
  • 88.00 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
85.37%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 11.360s 4614.974us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.910s 19217.786us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.970s 18.626us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.760s 25.249us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.960s 579.689us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.580s 117.017us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.060s 412.702us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.760s 25.249us 1 1 100.00
i2c_csr_aliasing 1.580s 117.017us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.930s 60.880us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 179.590s 13643.495us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 5.340s 766.875us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.770s 95.753us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 153.370s 17997.900us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 48.140s 3000.795us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.090s 156.305us 1 1 100.00
i2c_host_fifo_fmt_empty 12.890s 476.241us 1 1 100.00
i2c_host_fifo_reset_rx 4.410s 406.158us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 68.480s 4480.975us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 12.050s 734.361us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 1.440s 126.588us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 2.090s 3784.492us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 38.600s 35768.092us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.320s 424.634us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 10.510s 2452.293us 1 1 100.00
i2c_target_intr_smoke 3.640s 933.262us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.030s 323.190us 1 1 100.00
i2c_target_fifo_reset_tx 1.860s 226.978us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 805.390s 55171.371us 1 1 100.00
i2c_target_stress_rd 10.510s 2452.293us 1 1 100.00
i2c_target_intr_stress_wr 73.930s 20641.240us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.320s 12162.698us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1.800s 649.162us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.290s 2055.249us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 9.140s 10010.236us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.860s 574.739us 1 1 100.00
i2c_target_fifo_watermarks_tx 1.160s 163.457us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 5.340s 766.875us 1 1 100.00
i2c_host_perf_precise 1.400s 77.535us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 12.050s 734.361us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.550s 82.942us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 3.210s 1060.592us 1 1 100.00
i2c_target_nack_acqfull_addr 1.740s 1072.767us 1 1 100.00
i2c_target_nack_txstretch 1.570s 139.926us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 6.180s 561.189us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.740s 1648.862us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.780s 18.284us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.830s 25.357us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 2.260s 545.247us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 2.260s 545.247us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.970s 18.626us 1 1 100.00
i2c_csr_rw 0.760s 25.249us 1 1 100.00
i2c_csr_aliasing 1.580s 117.017us 1 1 100.00
i2c_same_csr_outstanding 0.930s 32.603us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.970s 18.626us 1 1 100.00
i2c_csr_rw 0.760s 25.249us 1 1 100.00
i2c_csr_aliasing 1.580s 117.017us 1 1 100.00
i2c_same_csr_outstanding 0.930s 32.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.340s 70.537us 1 1 100.00
i2c_sec_cm 1.170s 162.055us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.340s 70.537us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 23.880s 3602.769us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.440s 194.716us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 23.100s 874.809us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 68514895220069176855049588514055099642074010588444795518065504245862427271462 80
UVM_INFO @ 60880263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 34552530451953463226983946470542238447034068944368132435421682566461692425331 113
UVM_INFO @ 874809199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 2 test runs
i2c_host_stress_all 77546015522526680742455569547615234322966341882752268082555384092689355168518 148
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3046420
i2c_host_mode_toggle 103805097379652977657712175719863080605219965809075456122301140372954071081898 85
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @21631
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 101390562927718099677812229363033887445079048431703849234415493403406828879130 84
UVM_INFO @ 3784492499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 19718859801151593287379273819253779037844887919126835220736975414366069843391 78
UVM_INFO @ 194716122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! 1 test run
i2c_target_hrst 88253725599187160800456513702423329407076710345559890726948485559240896258805 79
UVM_INFO @ 10010236232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 18237459853037878744887687091789798176679681210855499714252242265547168888246 115
UVM_INFO @ 3602769065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * 1 test run
i2c_target_nack_txstretch 79930044071347901424569689649804539504677132985267621354150336680241722023530 78
UVM_INFO @ 139925779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---