Simulation Results: lc_ctrl/volatile_unlock_disabled

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.60 %
  • code
  • 83.83 %
  • assert
  • 94.97 %
  • func
  • 93.01 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 79.58 %
  • toggle
  • 83.95 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.160s 108.855us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.860s 60.045us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.860s 51.569us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.920s 1071.466us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 16.642us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.980s 82.499us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.860s 51.569us 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 16.642us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.900s 391.030us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.630s 412.019us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.030s 51.700us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.800s 38.966us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.290s 384.684us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_ctrl_prog_failure 1.800s 38.966us 1 1 100.00
lc_ctrl_errors 6.290s 384.684us 1 1 100.00
lc_ctrl_security_escalation 4.590s 1229.304us 1 1 100.00
lc_ctrl_jtag_state_failure 18.830s 2661.023us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.360s 1714.394us 1 1 100.00
lc_ctrl_jtag_errors 17.810s 3688.005us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.610s 371.916us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.630s 399.216us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.360s 1714.394us 1 1 100.00
lc_ctrl_jtag_errors 17.810s 3688.005us 1 1 100.00
lc_ctrl_jtag_access 4.230s 1388.571us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 10.880s 2464.879us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.320s 123.766us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.290s 357.945us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.600s 343.585us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.770s 602.453us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.020s 106.299us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.850s 106.833us 1 1 100.00
lc_ctrl_jtag_alert_test 1.820s 84.302us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.840s 461.474us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.770s 48.032us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 29.220s 3991.798us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.980s 27.416us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.840s 142.031us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.840s 142.031us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 60.045us 1 1 100.00
lc_ctrl_csr_rw 0.860s 51.569us 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 16.642us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.880s 49.042us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 60.045us 1 1 100.00
lc_ctrl_csr_rw 0.860s 51.569us 1 1 100.00
lc_ctrl_csr_aliasing 1.270s 16.642us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.880s 49.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.500s 469.201us 1 1 100.00
lc_ctrl_tl_intg_err 2.270s 202.169us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.270s 202.169us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.630s 412.019us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_ctrl_sec_cm 5.500s 469.201us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_ctrl_sec_cm 5.500s 469.201us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_ctrl_sec_cm 5.500s 469.201us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_ctrl_sec_cm 5.500s 469.201us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_ctrl_sec_cm 5.500s 469.201us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_ctrl_sec_cm 5.500s 469.201us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_ctrl_sec_cm 5.500s 469.201us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.720s 290.714us 1 1 100.00
lc_ctrl_sec_cm 5.500s 469.201us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.590s 1229.304us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.900s 391.030us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.630s 399.216us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.650s 1222.935us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.650s 1222.935us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.760s 516.774us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.780s 629.173us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.780s 629.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 19.530s 2906.330us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 83761155922868338065527726385119498110786112582485877880026071608321323654595 4988
UVM_INFO @ 2906330325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---