Simulation Results: lc_ctrl/volatile_unlock_enabled

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.10 %
  • code
  • 84.24 %
  • assert
  • 94.97 %
  • func
  • 94.09 %
  • line
  • 97.26 %
  • branch
  • 93.80 %
  • cond
  • 79.20 %
  • toggle
  • 85.54 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.080s 40.018us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.800s 52.792us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.770s 50.764us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.880s 436.175us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 25.892us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.170s 24.491us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.770s 50.764us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 25.892us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.330s 107.001us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.130s 1319.644us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.820s 39.115us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.010s 515.850us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.890s 989.596us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_ctrl_prog_failure 2.010s 515.850us 1 1 100.00
lc_ctrl_errors 4.890s 989.596us 1 1 100.00
lc_ctrl_security_escalation 4.150s 520.563us 1 1 100.00
lc_ctrl_jtag_state_failure 14.380s 1781.862us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.140s 1804.233us 1 1 100.00
lc_ctrl_jtag_errors 17.060s 8277.121us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.400s 568.116us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.810s 1335.673us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.140s 1804.233us 1 1 100.00
lc_ctrl_jtag_errors 17.060s 8277.121us 1 1 100.00
lc_ctrl_jtag_access 5.370s 691.788us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 5.880s 651.126us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.070s 112.051us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.050s 34.344us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.850s 471.263us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.410s 574.783us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.500s 43.947us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.430s 370.469us 1 1 100.00
lc_ctrl_jtag_alert_test 1.000s 287.280us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.750s 1879.588us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.800s 52.548us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 32.330s 3480.294us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.270s 24.763us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.650s 29.958us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.650s 29.958us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 52.792us 1 1 100.00
lc_ctrl_csr_rw 0.770s 50.764us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 25.892us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 515.100us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.800s 52.792us 1 1 100.00
lc_ctrl_csr_rw 0.770s 50.764us 1 1 100.00
lc_ctrl_csr_aliasing 1.110s 25.892us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.170s 515.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.160s 531.317us 1 1 100.00
lc_ctrl_tl_intg_err 2.530s 312.268us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.530s 312.268us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.130s 1319.644us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_ctrl_sec_cm 6.160s 531.317us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_ctrl_sec_cm 6.160s 531.317us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_ctrl_sec_cm 6.160s 531.317us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_ctrl_sec_cm 6.160s 531.317us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_ctrl_sec_cm 6.160s 531.317us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_ctrl_sec_cm 6.160s 531.317us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_ctrl_sec_cm 6.160s 531.317us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.640s 1235.652us 1 1 100.00
lc_ctrl_sec_cm 6.160s 531.317us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.150s 520.563us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.330s 107.001us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.810s 1335.673us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1457.372us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 1457.372us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.770s 1443.512us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.570s 473.528us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.570s 473.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 33.760s 12563.600us 1 1 100.00