Simulation Results: otbn

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.24 %
  • code
  • 86.25 %
  • assert
  • 90.00 %
  • func
  • 97.46 %
  • block
  • 99.24 %
  • line
  • 99.46 %
  • branch
  • 94.51 %
  • toggle
  • 84.85 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 41.644us 1 1 100.00
single_binary 1 1 100.00
otbn_single 32.000s 430.978us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 32.000s 36.350us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 33.000s 20.687us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 35.000s 565.029us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 33.000s 14.803us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 34.000s 268.661us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 33.000s 20.687us 1 1 100.00
otbn_csr_aliasing 33.000s 14.803us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 47.000s 5576.069us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 44.000s 1300.300us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 29.000s 328.528us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 55.000s 750.054us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 81.000s 750.788us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 69.000s 515.325us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 35.000s 31.077us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 70.247us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 33.504us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 33.000s 20.331us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 9.000s 115.814us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 194.684us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 194.684us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 32.000s 36.350us 1 1 100.00
otbn_csr_rw 33.000s 20.687us 1 1 100.00
otbn_csr_aliasing 33.000s 14.803us 1 1 100.00
otbn_same_csr_outstanding 6.000s 28.703us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 32.000s 36.350us 1 1 100.00
otbn_csr_rw 33.000s 20.687us 1 1 100.00
otbn_csr_aliasing 33.000s 14.803us 1 1 100.00
otbn_same_csr_outstanding 6.000s 28.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 25.000s 27.529us 1 1 100.00
otbn_dmem_err 37.000s 63.055us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 40.000s 122.628us 1 1 100.00
otbn_controller_ispr_rdata_err 44.000s 36.965us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 783.147us 1 1 100.00
otbn_urnd_err 5.000s 45.774us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 27.000s 17.714us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 8.000s 19.611us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 21.058us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
otbn_tl_intg_err 12.000s 266.903us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 41.000s 662.283us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 41.644us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 37.000s 63.055us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 25.000s 27.529us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 12.000s 266.903us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 35.000s 31.077us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 25.000s 27.529us 1 1 100.00
otbn_dmem_err 37.000s 63.055us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 70.247us 1 1 100.00
otbn_illegal_mem_acc 27.000s 17.714us 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 32.000s 430.978us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 25.000s 27.529us 1 1 100.00
otbn_dmem_err 37.000s 63.055us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 70.247us 1 1 100.00
otbn_illegal_mem_acc 27.000s 17.714us 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 35.000s 31.077us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 25.000s 27.529us 1 1 100.00
otbn_dmem_err 37.000s 63.055us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 70.247us 1 1 100.00
otbn_illegal_mem_acc 27.000s 17.714us 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 32.000s 430.978us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 38.000s 31.328us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 92.233us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 51.000s 402.565us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 51.000s 402.565us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 19.706us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 8.000s 106.859us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 7.000s 9.917us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 7.000s 9.917us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 10.534us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 32.000s 430.978us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 32.000s 430.978us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 32.000s 430.978us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 81.000s 750.788us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 32.000s 430.978us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 32.000s 430.978us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 160.466us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 32.000s 430.978us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 340.000s 14887.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 240.000s 3267.757us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 33.418us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
otbn_stress_all_with_rand_reset 5771735535710740854651050654030869189217345428396602165863344632198236859811 494
UVM_INFO @ 3267757231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 102480301451784383365756471119595091822109811324259635124699422171373967118212 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 9916965 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 9916965 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 9916965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---