Simulation Results: otp_ctrl

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.95 %
  • code
  • 78.27 %
  • assert
  • 94.70 %
  • func
  • 75.89 %
  • line
  • 88.45 %
  • branch
  • 83.26 %
  • cond
  • 89.99 %
  • toggle
  • 85.54 %
  • FSM
  • 44.10 %
Validation stages
V1
100.00%
V2
90.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.540s 204.744us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 6.170s 368.469us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.080s 131.537us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.320s 82.728us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.460s 1641.393us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.410s 158.927us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.480s 113.158us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.320s 82.728us 1 1 100.00
otp_ctrl_csr_aliasing 3.410s 158.927us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.190s 142.277us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.200s 41.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 25.960s 15031.839us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.050s 421.936us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 8.420s 3389.530us 1 1 100.00
otp_ctrl_check_fail 6.090s 302.504us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.270s 2046.913us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 21.820s 7794.351us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 6.860s 376.255us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 11.760s 2365.955us 1 1 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 31.120s 3469.792us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.410s 144.771us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 37.780s 23707.278us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 271.540s 92737.727us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.310s 40.598us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.670s 157.421us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.870s 234.759us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.870s 234.759us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.080s 131.537us 1 1 100.00
otp_ctrl_csr_rw 1.320s 82.728us 1 1 100.00
otp_ctrl_csr_aliasing 3.410s 158.927us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.950s 116.554us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.080s 131.537us 1 1 100.00
otp_ctrl_csr_rw 1.320s 82.728us 1 1 100.00
otp_ctrl_csr_aliasing 3.410s 158.927us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.950s 116.554us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
otp_ctrl_tl_intg_err 15.490s 2230.352us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 15.490s 2230.352us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 6.170s 368.469us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 6.170s 368.469us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
otp_ctrl_macro_errs 1.410s 144.771us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
otp_ctrl_macro_errs 1.410s 144.771us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 32.990s 18048.730us 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.050s 421.936us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 6.090s 302.504us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 21.820s 7794.351us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 21.820s 7794.351us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 21.820s 7794.351us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 21.820s 7794.351us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 21.820s 7794.351us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 6.170s 368.469us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 21.820s 7794.351us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 6.170s 368.469us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.610s 10979.145us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.270s 2046.913us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 6.170s 368.469us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 6.170s 368.469us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.410s 144.771us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 16.020s 8823.315us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 40.330s 2133.273us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 89112923146178878481194547348953878262711965740543392621089303519114785275244 7238
UVM_INFO @ 302504063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 85591478588959515696833126095189420502418177365352519417613215832152908833438 205
UVM_INFO @ 144771309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1831) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 88874537452263615655616534091871503819101006583017954458960119289402499566716 31499
UVM_INFO @ 2133273203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---