Simulation Results: pwrmgr

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.39 %
  • code
  • 97.35 %
  • assert
  • 97.13 %
  • func
  • 97.69 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 96.04 %
  • toggle
  • 99.44 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.740s 27.239us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.800s 44.507us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.670s 57.532us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.950s 397.261us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.920s 136.633us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.020s 112.181us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.670s 57.532us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 136.633us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.830s 399.739us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.830s 399.739us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 1.050s 60.039us 1 1 100.00
pwrmgr_lowpower_invalid 0.830s 40.644us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.890s 148.484us 1 1 100.00
pwrmgr_reset_invalid 1.170s 97.508us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.890s 148.484us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.790s 135.863us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.000s 158.509us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.820s 92.935us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.800s 153.721us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.580s 22.689us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.530s 87.786us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.530s 87.786us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.800s 44.507us 1 1 100.00
pwrmgr_csr_rw 0.670s 57.532us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 136.633us 1 1 100.00
pwrmgr_same_csr_outstanding 0.920s 74.551us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.800s 44.507us 1 1 100.00
pwrmgr_csr_rw 0.670s 57.532us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 136.633us 1 1 100.00
pwrmgr_same_csr_outstanding 0.920s 74.551us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.930s 145.151us 1 1 100.00
pwrmgr_sec_cm 0.940s 492.984us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 0.940s 492.984us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 0.940s 492.984us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.930s 145.151us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.750s 926.249us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.790s 135.863us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.770s 1229.157us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.980s 73.541us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.730s 43.549us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 0.940s 492.984us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 0.940s 492.984us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 0.940s 492.984us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.690s 79.020us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.720s 59.297us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.850s 92.261us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 57.532us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 57.532us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.870s 184.901us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 1.500s 2537.007us 0 1 0.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 8526759108121904522192114607892580699951141065552940562124681760298666497664 79
UVM_ERROR @ 184900828 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 184900828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
pwrmgr_stress_all_with_rand_reset 10451946447022271064858472147280785702226280845077322204420189129626717134341 464
UVM_INFO @ 2537006797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---