| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_max_throughput_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_err_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| rom_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| passthru_mem_tl_intg_err | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_fsm_local_esc | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_digest | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_local_esc | 0 | 2 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_mem_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 20 test runs | |||
| rom_ctrl_smoke | 14250957759236524716990633830506359097852730441744029577471538181878984455784 | None | ||
| rom_ctrl_stress_all | 78135960616906709879410084717362890502899538485222154055788978878009359750518 | None | ||
| rom_ctrl_max_throughput_chk | 32128578153540294513135338861112861124459718985777323149617648791259456263632 | None | ||
| rom_ctrl_corrupt_sig_fatal_chk | 109377775091412991145700909576082063464222394448104073387802706702028801143178 | None | ||
| rom_ctrl_kmac_err_chk | 66216629216563778564339959523888896508431897856659815452636677496094546976452 | None | ||
| rom_ctrl_stress_all_with_rand_reset | 66995333283685065993269411515310288265140082701945223904748911012703349288415 | None | ||
| rom_ctrl_sec_cm | 37964167904204804235251926774901346923987586483404661450777397344145105894081 | None | ||
| rom_ctrl_passthru_mem_tl_intg_err | 68319885861752432504387120277868105612359009733197447761310443179170898161864 | None | ||
| rom_ctrl_tl_errors | 50095381020359806947559884223601330800887702958666366403615735818600190591989 | None | ||
| rom_ctrl_tl_intg_err | 111500966866966396428377074494618599808488937204312509228546686802879346183939 | None | ||
| rom_ctrl_alert_test | 9799845306596042791896178515843152224886555954887251589565495594033319543900 | None | ||
| rom_ctrl_mem_walk | 71124545812673142596825073002318137729882028557464278074666956215808390020122 | None | ||
| rom_ctrl_mem_partial_access | 37318253708895043359286019279559268643739748743811516778249357980747307415270 | None | ||
| rom_ctrl_csr_hw_reset | 14038064912957527700210469156475062620982089688750428092772703672409098682607 | None | ||
| rom_ctrl_csr_rw | 65397390054372199791351396171700134960874275420279197147399344272739028070187 | None | ||
| rom_ctrl_csr_bit_bash | 9507261877267900279306735507577106926347858758658052560419539729719324737382 | None | ||
| rom_ctrl_csr_aliasing | 76748332324628640912662746638358916947428869100866756401876204105484719995533 | None | ||
| rom_ctrl_same_csr_outstanding | 59973532905524664500060751304583116709653559615826776962009788665803392861261 | None | ||
| rom_ctrl_csr_mem_rw_with_rand_reset | 54013215353297424944335433677067828142556676972883204014224836413768620083142 | None | ||
| rom_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/default/fusesoc-work/185949: No such file or directory.
/tmp/vcs_20260803153218_133982/.stack_annotator_gdb_cmd_file_l7gtCF:2: Error in sourced command file:
No stack.
Process VmPeak: 437092 kb, VmSize: 421488 kb
System Free Memory: 123654192 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 11.948 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/cover_reg_top/fusesoc-work/104618: No such file or directory.
/tmp/vcs_20260803153110_12484/.stack_annotator_gdb_cmd_file_bGIIY5:2: Error in sourced command file:
No stack.
Process VmPeak: 438000 kb, VmSize: 422396 kb
System Free Memory: 123185948 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 12.771 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| rom_ctrl | None | None | ||