Simulation Results: rv_timer

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.00 %
  • code
  • 94.59 %
  • assert
  • 96.82 %
  • func
  • 90.59 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.760s 514.590us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.680s 17.367us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 20.844us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.400s 192.169us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.940s 20.388us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.840s 33.026us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 20.844us 1 1 100.00
rv_timer_csr_aliasing 0.940s 20.388us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.600s 66.171us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.490s 4165.152us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 330.930s 706287.915us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 330.930s 706287.915us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.240s 1759.282us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.680s 12.712us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.610s 40.748us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.830s 130.316us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.830s 130.316us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 17.367us 1 1 100.00
rv_timer_csr_rw 0.550s 20.844us 1 1 100.00
rv_timer_csr_aliasing 0.940s 20.388us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 69.227us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 17.367us 1 1 100.00
rv_timer_csr_rw 0.550s 20.844us 1 1 100.00
rv_timer_csr_aliasing 0.940s 20.388us 1 1 100.00
rv_timer_same_csr_outstanding 0.680s 69.227us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.740s 65.115us 1 1 100.00
rv_timer_tl_intg_err 1.140s 248.714us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.140s 248.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.730s 75.613us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.730s 86.712us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 12.230s 4740.526us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 44512290393773370732624496027129897367892467674245334565153100355693649772149 75
UVM_INFO @ 75613490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 67643491241660022268718583423172895109553282903581966007717529193795380538408 75
UVM_INFO @ 66170620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 102956152485500906582755972500645940328648561965800892158366917389152984429235 75
UVM_INFO @ 86711581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 1 test run
rv_timer_stress_all_with_rand_reset 99745655382962467478358019901714349898659049729218570774271752184263644732362 216
UVM_INFO @ 4740526489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---