| V1 |
|
100.00% |
| V2 |
|
92.59% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 154.360s | 52341.941us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_hw_reset | 1.260s | 236.251us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_device_csr_rw | 1.010s | 21.755us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_device_csr_bit_bash | 8.730s | 1065.942us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_device_csr_aliasing | 15.280s | 1000.184us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_mem_rw_with_rand_reset | 2.530s | 200.302us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_device_csr_rw | 1.010s | 21.755us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 15.280s | 1000.184us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_device_mem_walk | 0.690s | 113.372us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_device_mem_partial_access | 1.400s | 53.831us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| csb_read | 1 | 1 | 100.00 | |||
| spi_device_csb_read | 0.810s | 40.203us | 1 | 1 | 100.00 | |
| mem_parity | 0 | 1 | 0.00 | |||
| spi_device_mem_parity | 0.720s | 2.760us | 0 | 1 | 0.00 | |
| mem_cfg | 0 | 1 | 0.00 | |||
| spi_device_ram_cfg | 0.800s | 3.675us | 0 | 1 | 0.00 | |
| tpm_read | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 2.880s | 1219.653us | 1 | 1 | 100.00 | |
| tpm_write | 1 | 1 | 100.00 | |||
| spi_device_tpm_rw | 2.880s | 1219.653us | 1 | 1 | 100.00 | |
| tpm_hw_reg | 2 | 2 | 100.00 | |||
| spi_device_tpm_read_hw_reg | 1.430s | 337.451us | 1 | 1 | 100.00 | |
| spi_device_tpm_sts_read | 0.720s | 104.636us | 1 | 1 | 100.00 | |
| tpm_fully_random_case | 1 | 1 | 100.00 | |||
| spi_device_tpm_all | 16.280s | 1971.797us | 1 | 1 | 100.00 | |
| pass_cmd_filtering | 2 | 2 | 100.00 | |||
| spi_device_pass_cmd_filtering | 7.410s | 14638.327us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| pass_addr_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 6.920s | 17583.873us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| pass_payload_translation | 2 | 2 | 100.00 | |||
| spi_device_pass_addr_payload_swap | 6.920s | 17583.873us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| cmd_info_slots | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| cmd_read_status | 2 | 2 | 100.00 | |||
| spi_device_intercept | 5.430s | 1267.306us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| cmd_read_jedec | 2 | 2 | 100.00 | |||
| spi_device_intercept | 5.430s | 1267.306us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| cmd_read_sfdp | 2 | 2 | 100.00 | |||
| spi_device_intercept | 5.430s | 1267.306us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| cmd_fast_read | 2 | 2 | 100.00 | |||
| spi_device_intercept | 5.430s | 1267.306us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| cmd_read_pipeline | 2 | 2 | 100.00 | |||
| spi_device_intercept | 5.430s | 1267.306us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| flash_cmd_upload | 1 | 1 | 100.00 | |||
| spi_device_upload | 3.100s | 718.753us | 1 | 1 | 100.00 | |
| mailbox_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 23.820s | 12855.894us | 1 | 1 | 100.00 | |
| mailbox_cross_outside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 23.820s | 12855.894us | 1 | 1 | 100.00 | |
| mailbox_cross_inside_command | 1 | 1 | 100.00 | |||
| spi_device_mailbox | 23.820s | 12855.894us | 1 | 1 | 100.00 | |
| cmd_read_buffer | 2 | 2 | 100.00 | |||
| spi_device_flash_mode | 2.590s | 370.097us | 1 | 1 | 100.00 | |
| spi_device_read_buffer_direct | 3.290s | 396.183us | 1 | 1 | 100.00 | |
| cmd_dummy_cycle | 2 | 2 | 100.00 | |||
| spi_device_mailbox | 23.820s | 12855.894us | 1 | 1 | 100.00 | |
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| quad_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| dual_spi | 1 | 1 | 100.00 | |||
| spi_device_flash_all | 52.290s | 12756.961us | 1 | 1 | 100.00 | |
| 4b_3b_feature | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 3.630s | 1364.943us | 1 | 1 | 100.00 | |
| write_enable_disable | 1 | 1 | 100.00 | |||
| spi_device_cfg_cmd | 3.630s | 1364.943us | 1 | 1 | 100.00 | |
| flash_mode_ignore_cmds | 1 | 1 | 100.00 | |||
| spi_device_flash_mode_ignore_cmds | 91.960s | 122428.015us | 1 | 1 | 100.00 | |
| TPM_with_flash_or_passthrough_mode | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm | 154.360s | 52341.941us | 1 | 1 | 100.00 | |
| tpm_and_flash_trans_with_min_inactive_time | 1 | 1 | 100.00 | |||
| spi_device_flash_and_tpm_min_idle | 12.290s | 2656.955us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_device_stress_all | 0.860s | 189.899us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_device_alert_test | 0.750s | 40.929us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| spi_device_intr_test | 0.650s | 30.135us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.530s | 205.676us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_device_tl_errors | 3.530s | 205.676us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 1.260s | 236.251us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 1.010s | 21.755us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 15.280s | 1000.184us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 1.870s | 88.359us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| spi_device_csr_hw_reset | 1.260s | 236.251us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 1.010s | 21.755us | 1 | 1 | 100.00 | |
| spi_device_csr_aliasing | 15.280s | 1000.184us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 1.870s | 88.359us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| spi_device_sec_cm | 0.910s | 77.662us | 1 | 1 | 100.00 | |
| spi_device_tl_intg_err | 6.020s | 699.492us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| spi_device_tl_intg_err | 6.020s | 699.492us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) | 1 test run | |||
| spi_device_mem_parity | 59088349268325557773858482283018674354614336936578426532539138332979509884448 | 76 |
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2208537 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2208537 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[986])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
|
|
| UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) | 1 test run | |||
| spi_device_ram_cfg | 85218181292298892863918084627388192354573717304497212497498167959061442952522 | 76 |
UVM_ERROR @ 1301488 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x170 [101110000] vs 0x0 [0])
UVM_ERROR @ 1379488 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x18f [110001111] vs 0x0 [0])
UVM_ERROR @ 1433488 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3f9 [1111111001] vs 0x0 [0])
UVM_ERROR @ 1527488 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x333 [1100110011] vs 0x0 [0])
|
|