Simulation Results: sysrst_ctrl

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.77 %
  • code
  • 94.06 %
  • assert
  • 95.98 %
  • func
  • 67.27 %
  • line
  • 97.90 %
  • branch
  • 97.89 %
  • cond
  • 95.66 %
  • toggle
  • 100.00 %
  • FSM
  • 78.85 %
Validation stages
V1
100.00%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.170s 2134.302us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.940s 2474.893us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.720s 2448.798us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.520s 2351.033us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.870s 6248.908us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.350s 2059.465us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 30.640s 52624.021us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.620s 2492.315us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.450s 2060.629us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.350s 2059.465us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.620s 2492.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 31.240s 69680.634us 1 1 100.00
combo_detect_with_pre_cond 0 1 0.00
sysrst_ctrl_combo_detect_with_pre_cond 30.280s 29442.439us 0 1 0.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 5.050s 3205.078us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 6.800s 5615.690us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.530s 2526.443us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.600s 2200.600us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.260s 3214.770us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 1.400s 2708.115us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 3.920s 4313.659us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 15.840s 37221.219us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 32.550s 84549.897us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.620s 2031.632us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.710s 2013.228us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 6.400s 2118.806us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 6.400s 2118.806us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.870s 6248.908us 1 1 100.00
sysrst_ctrl_csr_rw 4.350s 2059.465us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.620s 2492.315us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.120s 4615.943us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.870s 6248.908us 1 1 100.00
sysrst_ctrl_csr_rw 4.350s 2059.465us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.620s 2492.315us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.120s 4615.943us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 33.480s 22013.397us 1 1 100.00
sysrst_ctrl_tl_intg_err 9.380s 22684.197us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 9.380s 22684.197us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.250s 9958.680us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(3) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 94136898334975823864293808235642929644944122718653817437118467782646921114434 679
UVM_ERROR @ 29442439211 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4
UVM_INFO @ 29442439211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---