Simulation Results: uart

 
03/08/2026 15:30:55 DVSim: v1.50.0 sha: 2719cd7 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.19 %
  • code
  • 92.55 %
  • assert
  • 97.12 %
  • func
  • 56.90 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.90 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.150s 498.221us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.580s 25.428us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.550s 15.995us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.320s 1536.290us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.720s 40.849us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.690s 73.599us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.550s 15.995us 1 1 100.00
uart_csr_aliasing 0.720s 40.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 9.140s 69805.858us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.150s 498.221us 1 1 100.00
uart_tx_rx 9.140s 69805.858us 1 1 100.00
parity_error 2 2 100.00
uart_intr 5.070s 25121.411us 1 1 100.00
uart_rx_parity_err 20.830s 63132.079us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 9.140s 69805.858us 1 1 100.00
uart_intr 5.070s 25121.411us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 34.780s 38603.979us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 4.640s 37257.852us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 6.460s 37597.073us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 5.070s 25121.411us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 5.070s 25121.411us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 5.070s 25121.411us 1 1 100.00
perf 1 1 100.00
uart_perf 367.590s 15673.058us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 14.160s 11624.191us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 14.160s 11624.191us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 9.530s 20045.035us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 36.150s 46506.673us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.850s 934.004us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 9.080s 7261.623us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 360.260s 66335.855us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 97.060s 283779.159us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.710s 12.441us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.650s 24.105us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.260s 118.691us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.260s 118.691us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.580s 25.428us 1 1 100.00
uart_csr_rw 0.550s 15.995us 1 1 100.00
uart_csr_aliasing 0.720s 40.849us 1 1 100.00
uart_same_csr_outstanding 0.730s 118.303us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.580s 25.428us 1 1 100.00
uart_csr_rw 0.550s 15.995us 1 1 100.00
uart_csr_aliasing 0.720s 40.849us 1 1 100.00
uart_same_csr_outstanding 0.730s 118.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.090s 38.144us 1 1 100.00
uart_tl_intg_err 0.940s 202.358us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.940s 202.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 4.710s 3778.905us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 85424250104844850064328730873171431531648664368985388798901138375676359948421 77
UVM_ERROR @ 19291234246 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 14, clk_pulses: 0
UVM_ERROR @ 19291275912 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 19291296745 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 19291338411 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty