Simulation Results: adc_ctrl

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.23 %
  • code
  • 93.68 %
  • assert
  • 91.90 %
  • func
  • 13.12 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 86.06 %
  • toggle
  • 98.82 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.850s 5942.605us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.210s 1235.807us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.850s 572.043us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 41.900s 27016.241us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.570s 870.094us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.080s 513.083us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.850s 572.043us 1 1 100.00
adc_ctrl_csr_aliasing 1.570s 870.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.870s 510.394us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.760s 467.150us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.750s 500.244us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.740s 501.216us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.170s 433.219us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 1.210s 525.312us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.870s 458.121us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.710s 467.049us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.810s 3616.561us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 58.550s 44150.640us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 170.690s 114731.422us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 3.210s 6813.664us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.230s 522.458us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.800s 356.170us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.580s 475.222us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.580s 475.222us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.210s 1235.807us 1 1 100.00
adc_ctrl_csr_rw 0.850s 572.043us 1 1 100.00
adc_ctrl_csr_aliasing 1.570s 870.094us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.620s 5037.309us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.210s 1235.807us 1 1 100.00
adc_ctrl_csr_rw 0.850s 572.043us 1 1 100.00
adc_ctrl_csr_aliasing 1.570s 870.094us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.620s 5037.309us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.150s 4179.051us 1 1 100.00
adc_ctrl_tl_intg_err 3.320s 9110.247us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.320s 9110.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 2.650s 1567.666us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 81377470407285449077227063942613052592543636106848557233834916990602532153811 386
UVM_INFO @ 510394227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 107358216212260500288760139216006647302128203900645239632368319888371601817551 386
UVM_INFO @ 467150354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 112248658289802428200834144550565898805604504358335994597414153510566866418823 386
UVM_INFO @ 500243589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 107258752915198535187998087773085003998931993816411132173139459287280987176066 386
UVM_INFO @ 501216212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 65842222690767659042256848366591944480311098141874304288190834126897172406630 386
UVM_INFO @ 433218725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 113520605094681524511998523107289321651437982105781378094168095238011717302360 386
UVM_INFO @ 525312375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 34759155701528930866798502218737792134136676286978775715487741986222293861180 386
UVM_INFO @ 467048764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 111956114952495955991890116148214204761755130017460785340101249832616541099814 386
UVM_INFO @ 458121498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 68615790703186168758701665500543767800546210243878779566834225728626543952212 416
UVM_INFO @ 1567666449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 9910768960007844552204779811091283302237662811513576422546602218821445008571 402
UVM_INFO @ 6813663862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---