Simulation Results: aes/unmasked

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.00 %
  • code
  • 88.94 %
  • assert
  • 97.73 %
  • func
  • 71.32 %
  • block
  • 89.23 %
  • line
  • 91.77 %
  • branch
  • 79.31 %
  • toggle
  • 97.99 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
94.12%
V2S
81.25%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 117.535us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 68.953us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 69.624us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 77.476us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 1811.496us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 120.225us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 79.824us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 77.476us 1 1 100.00
aes_csr_aliasing 3.000s 120.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 68.953us 1 1 100.00
aes_config_error 2.000s 262.738us 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 68.953us 1 1 100.00
aes_config_error 2.000s 262.738us 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 121.437us 1 1 100.00
aes_b2b 3.000s 67.763us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 1.000s 68.953us 1 1 100.00
aes_config_error 2.000s 262.738us 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
aes_alert_reset 2.000s 113.265us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 113.904us 1 1 100.00
aes_config_error 2.000s 262.738us 1 1 100.00
aes_alert_reset 2.000s 113.265us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 72.561us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 215.095us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 113.265us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 121.437us 1 1 100.00
aes_sideload 3.000s 109.612us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 1.000s 63.408us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 11.000s 260.660us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 56.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 79.449us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 79.449us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 69.624us 1 1 100.00
aes_csr_rw 2.000s 77.476us 1 1 100.00
aes_csr_aliasing 3.000s 120.225us 1 1 100.00
aes_same_csr_outstanding 2.000s 82.092us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 69.624us 1 1 100.00
aes_csr_rw 2.000s 77.476us 1 1 100.00
aes_csr_aliasing 3.000s 120.225us 1 1 100.00
aes_same_csr_outstanding 2.000s 82.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 37.837us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 2.000s 133.828us 0 1 0.00
aes_control_fi 1.000s 112.897us 1 1 100.00
aes_cipher_fi 2.000s 52.885us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 115.382us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 115.382us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 115.382us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 115.382us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 76.693us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 1003.195us 1 1 100.00
aes_tl_intg_err 2.000s 154.969us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 154.969us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 113.265us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 115.382us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 115.382us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 1.000s 68.953us 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
aes_alert_reset 2.000s 113.265us 1 1 100.00
aes_core_fi 18.000s 10004.535us 0 1 0.00
sec_cm_gcm_config_sparse 2 3 66.67
aes_config_error 2.000s 262.738us 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
aes_core_fi 18.000s 10004.535us 0 1 0.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 115.382us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 160.656us 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 121.437us 1 1 100.00
aes_sideload 3.000s 109.612us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 160.656us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 160.656us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 160.656us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 160.656us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 160.656us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 121.437us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 133.828us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 133.828us 0 1 0.00
aes_control_fi 1.000s 112.897us 1 1 100.00
aes_cipher_fi 2.000s 52.885us 1 1 100.00
aes_ctr_fi 2.000s 75.797us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 133.828us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 133.828us 0 1 0.00
aes_control_fi 1.000s 112.897us 1 1 100.00
aes_cipher_fi 2.000s 52.885us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 52.885us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 133.828us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 133.828us 0 1 0.00
aes_control_fi 1.000s 112.897us 1 1 100.00
aes_ctr_fi 2.000s 75.797us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 133.828us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 133.828us 0 1 0.00
aes_control_fi 1.000s 112.897us 1 1 100.00
aes_cipher_fi 2.000s 52.885us 1 1 100.00
aes_ctr_fi 2.000s 75.797us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 113.265us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 133.828us 0 1 0.00
aes_control_fi 1.000s 112.897us 1 1 100.00
aes_cipher_fi 2.000s 52.885us 1 1 100.00
aes_ctr_fi 2.000s 75.797us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 133.828us 0 1 0.00
aes_control_fi 1.000s 112.897us 1 1 100.00
aes_cipher_fi 2.000s 52.885us 1 1 100.00
aes_ctr_fi 2.000s 75.797us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 133.828us 0 1 0.00
aes_control_fi 1.000s 112.897us 1 1 100.00
aes_ctr_fi 2.000s 75.797us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 133.828us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 133.828us 0 1 0.00
aes_control_fi 1.000s 112.897us 1 1 100.00
aes_cipher_fi 2.000s 52.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 7.000s 346.914us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 98815485063252934490991534741801721431455981607432056708601301274381327940700 2390
UVM_INFO @ 37836964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 89591099242697678417718426176515508953184695198062624763677799629146651875767 38186
UVM_INFO @ 260659959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 57752633982940633603359320820246429120233030553783932333372306476925499176395 10335
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 10611882117387969351338014503578595640354273322697633784581363301056042499906 147
UVM_INFO @ 10004534748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 30416754214844955730586825674894299512662735195309689647085795614283530280584 304
UVM_INFO @ 346914488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---