Simulation Results: alert_handler

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.21 %
  • code
  • 90.84 %
  • assert
  • 98.27 %
  • func
  • 78.53 %
  • line
  • 99.69 %
  • branch
  • 98.47 %
  • cond
  • 91.16 %
  • toggle
  • 89.07 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 24.510s 1566.195us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.720s 102.493us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.910s 489.678us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 377.390s 11719.126us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 180.320s 9565.255us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.720s 250.828us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.910s 489.678us 1 1 100.00
alert_handler_csr_aliasing 180.320s 9565.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 266.120s 16309.124us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 6.830s 162.439us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1864.380s 98466.621us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 17.260s 275.540us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 24.510s 1566.195us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 17.120s 352.807us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 15.200s 390.401us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 323.130s 49028.332us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 733.830s 69747.068us 1 1 100.00
alert_handler_lpg_stub_clk 963.510s 17064.159us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1769.150s 32076.212us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 4.980s 171.674us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.640s 186.510us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.090s 14.512us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 9.220s 199.846us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 9.220s 199.846us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.720s 102.493us 1 1 100.00
alert_handler_csr_rw 5.910s 489.678us 1 1 100.00
alert_handler_csr_aliasing 180.320s 9565.255us 1 1 100.00
alert_handler_same_csr_outstanding 15.140s 1246.183us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.720s 102.493us 1 1 100.00
alert_handler_csr_rw 5.910s 489.678us 1 1 100.00
alert_handler_csr_aliasing 180.320s 9565.255us 1 1 100.00
alert_handler_same_csr_outstanding 15.140s 1246.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 105.940s 5186.191us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 105.940s 5186.191us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 105.940s 5186.191us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 105.940s 5186.191us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 838.540s 35260.514us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
alert_handler_tl_intg_err 3.010s 164.760us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 3.010s 164.760us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 105.940s 5186.191us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 24.510s 1566.195us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 24.510s 1566.195us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 24.510s 1566.195us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 24.510s 1566.195us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 17.260s 275.540us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 733.830s 69747.068us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 17.260s 275.540us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1864.380s 98466.621us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1864.380s 98466.621us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 8.240s 475.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 13.190s 589.339us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 6058168384675772166393968532335987363279424324949840150534627316189043770115 156
UVM_INFO @ 49028332176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 32003818885629175082468885372873837658942320768864294725553872349714776183463 206
UVM_INFO @ 171673508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 75907818978565801973262923746942899951473834302422724081381262681791957054932 101
UVM_INFO @ 589339355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---