Simulation Results: chip

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.29 %
  • code
  • 81.67 %
  • assert
  • 97.25 %
  • func
  • 40.95 %
  • line
  • 94.36 %
  • branch
  • 94.39 %
  • cond
  • 89.37 %
  • toggle
  • 73.09 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
88.45%
V2S
100.00%
V3
61.54%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 178.210s 3739.495us 1 1 100.00
chip_sw_example_rom 84.840s 2792.491us 1 1 100.00
chip_sw_example_manufacturer 184.500s 3797.666us 1 1 100.00
chip_sw_example_concurrency 186.150s 3272.303us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 191.750s 5540.081us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 421.600s 5347.992us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 861.480s 11908.838us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3826.610s 26525.575us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 469.460s 7475.474us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3826.610s 26525.575us 1 1 100.00
chip_csr_rw 421.600s 5347.992us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 5.150s 196.742us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 309.130s 5137.450us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 309.130s 5137.450us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 309.130s 5137.450us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 313.440s 5227.510us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 313.440s 5227.510us 1 1 100.00
chip_sw_uart_tx_rx_idx1 365.210s 5390.283us 1 1 100.00
chip_sw_uart_tx_rx_idx2 341.440s 4863.048us 1 1 100.00
chip_sw_uart_tx_rx_idx3 318.230s 5104.948us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1222.870s 9901.648us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 432.010s 3777.037us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 235.360s 4629.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 344.020s 6809.036us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 344.020s 6809.036us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 145.380s 4149.239us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 295.440s 7792.484us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 192.110s 4694.815us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 137.780s 3130.792us 1 1 100.00
chip_tap_straps_testunlock0 251.410s 5331.276us 1 1 100.00
chip_tap_straps_rma 427.320s 5993.637us 1 1 100.00
chip_tap_straps_prod 550.650s 9143.627us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 471.960s 6722.161us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 471.960s 6722.161us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 718.200s 8485.782us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1289.930s 12780.473us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 331.310s 3853.952us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 587.250s 6443.262us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4310.420s 19041.515us 1 1 100.00
chip_sw_aes_enc_jitter_en 218.770s 3681.624us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 843.920s 9414.334us 1 1 100.00
chip_sw_hmac_enc_jitter_en 160.150s 3632.922us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1483.850s 11944.790us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 196.450s 3495.724us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 292.570s 4942.253us 1 1 100.00
chip_sw_clkmgr_jitter 237.910s 3639.844us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 173.120s 3424.680us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 378.630s 7828.022us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 209.430s 5943.613us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 137.420s 3288.820us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 209.430s 5943.613us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 204.910s 3911.738us 1 1 100.00
chip_sw_aes_smoketest 192.670s 3643.269us 1 1 100.00
chip_sw_aon_timer_smoketest 244.140s 3815.410us 1 1 100.00
chip_sw_clkmgr_smoketest 219.770s 3104.031us 1 1 100.00
chip_sw_csrng_smoketest 177.360s 3453.998us 1 1 100.00
chip_sw_entropy_src_smoketest 670.250s 6047.242us 1 1 100.00
chip_sw_gpio_smoketest 211.620s 4193.784us 1 1 100.00
chip_sw_hmac_smoketest 203.860s 3502.328us 1 1 100.00
chip_sw_kmac_smoketest 226.510s 3970.902us 1 1 100.00
chip_sw_otbn_smoketest 622.900s 7636.648us 1 1 100.00
chip_sw_pwrmgr_smoketest 268.740s 7501.152us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 268.130s 8444.771us 1 1 100.00
chip_sw_rv_plic_smoketest 119.860s 4026.029us 1 1 100.00
chip_sw_rv_timer_smoketest 135.570s 4218.899us 1 1 100.00
chip_sw_rstmgr_smoketest 151.890s 3469.482us 1 1 100.00
chip_sw_sram_ctrl_smoketest 124.760s 3128.502us 1 1 100.00
chip_sw_uart_smoketest 183.970s 3629.377us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 200.820s 4235.978us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 334.640s 5248.820us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 9461.080s 60303.845us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3579.890s 17373.146us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 991.590s 25939.707us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 909.570s 15785.704us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 521.620s 15280.920us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7709.330s 54862.097us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 9067.100s 57598.099us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 66.610s 3012.555us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 66.610s 3012.555us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3826.610s 26525.575us 1 1 100.00
chip_same_csr_outstanding 1010.220s 14093.112us 1 1 100.00
chip_csr_hw_reset 191.750s 5540.081us 1 1 100.00
chip_csr_rw 421.600s 5347.992us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3826.610s 26525.575us 1 1 100.00
chip_same_csr_outstanding 1010.220s 14093.112us 1 1 100.00
chip_csr_hw_reset 191.750s 5540.081us 1 1 100.00
chip_csr_rw 421.600s 5347.992us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 25.010s 501.585us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 3.810s 41.909us 1 1 100.00
xbar_smoke_large_delays 40.460s 7154.380us 1 1 100.00
xbar_smoke_slow_rsp 31.770s 3772.126us 1 1 100.00
xbar_random_zero_delays 6.710s 84.523us 1 1 100.00
xbar_random_large_delays 197.540s 34908.121us 1 1 100.00
xbar_random_slow_rsp 150.570s 17278.038us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 13.060s 159.245us 1 1 100.00
xbar_error_and_unmapped_addr 26.100s 1096.834us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 16.070s 308.295us 1 1 100.00
xbar_error_and_unmapped_addr 26.100s 1096.834us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 50.610s 1755.602us 1 1 100.00
xbar_access_same_device_slow_rsp 372.750s 44979.266us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 8.500s 164.143us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 78.300s 3084.242us 1 1 100.00
xbar_stress_all_with_error 24.900s 1231.648us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 344.890s 10494.137us 1 1 100.00
xbar_stress_all_with_reset_error 128.190s 4775.645us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3579.890s 17373.146us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2914.440s 26451.540us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 3286.650s 16127.665us 1 1 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2637.020s 13858.473us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 3540.330s 17462.517us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 3630.380s 16599.693us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 3672.160s 17784.848us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 3184.780s 16099.483us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 2734.030s 12859.537us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3608.800s 18043.620us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 3402.960s 16772.410us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 3619.530s 16241.474us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 3451.400s 19251.790us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 4690.340s 18153.642us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 6373.130s 24821.815us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 6027.330s 25281.564us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 6355.380s 25241.850us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 5802.560s 22972.094us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 4760.940s 18292.301us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 5774.930s 23392.426us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 5811.580s 23598.943us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 5987.480s 23279.492us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 5514.280s 22342.171us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 2438.810s 11208.903us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 3334.720s 15571.912us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 3347.180s 17223.497us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 3284.340s 15777.069us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 3333.250s 17179.366us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 2525.850s 11989.227us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 3262.310s 15481.526us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 3381.380s 15173.608us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 3212.270s 17622.609us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 3158.430s 14786.511us 1 1 100.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2617.130s 12495.255us 1 1 100.00
rom_e2e_asm_init_dev 3572.990s 15967.587us 1 1 100.00
rom_e2e_asm_init_prod 3711.250s 16674.598us 1 1 100.00
rom_e2e_asm_init_prod_end 3638.780s 15897.577us 1 1 100.00
rom_e2e_asm_init_rma 3425.040s 15377.833us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 6604.090s 29677.655us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 3544.200s 18576.473us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 6638.250s 30598.073us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3804.500s 17221.427us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3038.640s 35946.950us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3038.640s 35946.950us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 213.050s 3755.643us 1 1 100.00
chip_sw_aes_enc_jitter_en 218.770s 3681.624us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 203.070s 3555.971us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 217.890s 4246.296us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1174.930s 11753.859us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 243.320s 3926.844us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 460.640s 6429.496us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 401.010s 6298.303us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 627.440s 5902.884us 1 1 100.00
chip_plic_all_irqs_10 312.440s 4800.769us 1 1 100.00
chip_plic_all_irqs_20 432.410s 4377.278us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 255.060s 3392.330us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1088.740s 16114.048us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 293.860s 4392.763us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 196.960s 3188.354us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.156s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1082.240s 8571.593us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1302.570s 8717.334us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 854.150s 9262.127us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 9230.500s 255622.114us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 265.530s 4073.151us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 268.740s 7501.152us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 265.530s 4073.151us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 445.570s 7393.764us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 445.570s 7393.764us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 330.840s 8777.741us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 485.830s 6306.863us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 540.500s 6747.317us 1 1 100.00
chip_sw_aes_idle 217.890s 4246.296us 1 1 100.00
chip_sw_hmac_enc_idle 175.610s 3584.137us 1 1 100.00
chip_sw_kmac_idle 144.760s 3966.932us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 262.460s 4398.949us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 329.690s 6172.404us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 258.340s 4331.897us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 419.100s 7005.470us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 1023.600s 16723.970us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 471.040s 4959.721us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 421.970s 5235.311us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 475.980s 4043.413us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 487.550s 5896.997us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 467.390s 5179.208us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 391.520s 4613.446us 1 1 100.00
chip_sw_ast_clk_outputs 718.200s 8485.782us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 385.080s 6327.346us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 475.980s 4043.413us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 487.550s 5896.997us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 331.310s 3853.952us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 587.250s 6443.262us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4310.420s 19041.515us 1 1 100.00
chip_sw_aes_enc_jitter_en 218.770s 3681.624us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 843.920s 9414.334us 1 1 100.00
chip_sw_hmac_enc_jitter_en 160.150s 3632.922us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1483.850s 11944.790us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 196.450s 3495.724us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 292.570s 4942.253us 1 1 100.00
chip_sw_clkmgr_jitter 237.910s 3639.844us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 180.900s 3399.937us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 412.110s 5000.857us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 609.000s 7190.377us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4593.830s 25845.944us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 199.700s 3422.803us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 145.780s 4187.955us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 885.400s 11944.932us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 160.230s 4005.836us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 339.800s 6764.070us 1 1 100.00
chip_sw_flash_init_reduced_freq 1234.080s 28640.575us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 9973.930s 78921.044us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 718.200s 8485.782us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 444.660s 5507.007us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 320.580s 4614.954us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 401.010s 6298.303us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1082.240s 8571.593us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1304.910s 7483.099us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 365.800s 6134.377us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 535.470s 10461.667us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 192.570s 2800.108us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3077.190s 18014.311us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 177.860s 3013.320us 1 1 100.00
chip_sw_edn_entropy_reqs 749.710s 9031.095us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 177.860s 3013.320us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1304.910s 7483.099us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 190.060s 3633.503us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1204.890s 20897.006us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 560.900s 6379.700us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 587.250s 6443.262us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 369.010s 4486.752us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 331.310s 3853.952us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3810.800s 43969.608us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1204.890s 20897.006us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 226.760s 3753.257us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1035.810s 12141.449us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 220.260s 2817.210us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3810.800s 43969.608us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 220.260s 2817.210us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 220.260s 2817.210us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 220.260s 2817.210us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 220.260s 2817.210us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 401.010s 6298.303us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 268.800s 8510.732us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 523.070s 6117.380us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 407.810s 5384.127us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 407.810s 5384.127us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 144.090s 2736.802us 1 1 100.00
chip_sw_hmac_enc_jitter_en 160.150s 3632.922us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 175.610s 3584.137us 1 1 100.00
chip_sw_hmac_all_configurations 0 1 0.00
chip_sw_hmac_oneshot 1475.130s 12018.637us 0 1 0.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1414.240s 12026.735us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 403.170s 6240.996us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 418.280s 5385.117us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 320.190s 5099.121us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 218.490s 4801.219us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1035.810s 12141.449us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1483.850s 11944.790us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 734.450s 8844.335us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1174.930s 11753.859us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4764.140s 20018.696us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 196.850s 4412.088us 1 1 100.00
chip_sw_kmac_mode_kmac 219.250s 4305.996us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 196.450s 3495.724us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1035.810s 12141.449us 1 1 100.00
chip_sw_kmac_app_lc 0 1 0.00
chip_sw_lc_ctrl_transition 737.250s 27124.391us 0 1 0.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 167.850s 3390.580us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1101.560s 10044.265us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 144.760s 3966.932us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 460.640s 6429.496us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 137.780s 3130.792us 1 1 100.00
chip_tap_straps_rma 427.320s 5993.637us 1 1 100.00
chip_tap_straps_prod 550.650s 9143.627us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 157.060s 3016.814us 1 1 100.00
chip_sw_lc_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 737.250s 27124.391us 0 1 0.00
chip_sw_lc_ctrl_transitions 0 1 0.00
chip_sw_lc_ctrl_transition 737.250s 27124.391us 0 1 0.00
chip_sw_lc_ctrl_kmac_req 0 1 0.00
chip_sw_lc_ctrl_transition 737.250s 27124.391us 0 1 0.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 676.560s 8522.525us 1 1 100.00
chip_sw_lc_ctrl_broadcast 18 22 81.82
chip_sw_flash_ctrl_lc_rw_en 220.260s 2817.210us 0 1 0.00
chip_sw_flash_rma_unlocked 3810.800s 43969.608us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 208.810s 4185.567us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 476.870s 8625.048us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 581.310s 8141.005us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 547.840s 10000.486us 0 1 0.00
chip_sw_lc_ctrl_transition 737.250s 27124.391us 0 1 0.00
chip_sw_keymgr_key_derivation 1035.810s 12141.449us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 310.270s 9956.572us 1 1 100.00
chip_sw_sram_ctrl_execution_main 599.210s 12180.955us 1 1 100.00
chip_prim_tl_access 268.800s 8510.732us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 385.080s 6327.346us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 471.040s 4959.721us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 421.970s 5235.311us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 475.980s 4043.413us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 487.550s 5896.997us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 467.390s 5179.208us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 391.520s 4613.446us 1 1 100.00
chip_tap_straps_dev 137.780s 3130.792us 1 1 100.00
chip_tap_straps_rma 427.320s 5993.637us 1 1 100.00
chip_tap_straps_prod 550.650s 9143.627us 1 1 100.00
chip_rv_dm_lc_disabled 199.300s 6199.266us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 154.210s 4268.736us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 95.490s 4141.845us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 115.970s 4493.332us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 100.590s 3889.676us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1933.970s 36520.195us 1 1 100.00
chip_rv_dm_lc_disabled 199.300s 6199.266us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 929.500s 14206.658us 0 1 0.00
chip_sw_lc_walkthrough_prod 918.350s 15742.646us 0 1 0.00
chip_sw_lc_walkthrough_prodend 682.700s 14800.298us 1 1 100.00
chip_sw_lc_walkthrough_rma 475.860s 6810.248us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1933.970s 36520.195us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 96.410s 2863.588us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 77.080s 2901.851us 1 1 100.00
rom_volatile_raw_unlock 90.470s 3256.865us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 4110.830s 18448.644us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4310.420s 19041.515us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 540.500s 6747.317us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 540.500s 6747.317us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 540.500s 6747.317us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 257.040s 4352.729us 1 1 100.00
chip_otp_ctrl_init 0 1 0.00
chip_sw_lc_ctrl_transition 737.250s 27124.391us 0 1 0.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1204.890s 20897.006us 1 1 100.00
chip_sw_otbn_mem_scramble 257.040s 4352.729us 1 1 100.00
chip_sw_keymgr_key_derivation 1035.810s 12141.449us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 346.200s 5815.243us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 157.900s 3358.158us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1204.890s 20897.006us 1 1 100.00
chip_sw_otbn_mem_scramble 257.040s 4352.729us 1 1 100.00
chip_sw_keymgr_key_derivation 1035.810s 12141.449us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 346.200s 5815.243us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 157.900s 3358.158us 1 1 100.00
chip_sw_otp_ctrl_program 0 1 0.00
chip_sw_lc_ctrl_transition 737.250s 27124.391us 0 1 0.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 390.020s 5449.303us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 157.060s 3016.814us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 4 6 66.67
chip_sw_otp_ctrl_lc_signals_test_unlocked0 208.810s 4185.567us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 476.870s 8625.048us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 581.310s 8141.005us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 547.840s 10000.486us 0 1 0.00
chip_sw_lc_ctrl_transition 737.250s 27124.391us 0 1 0.00
chip_prim_tl_access 268.800s 8510.732us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 268.800s 8510.732us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 915.980s 8376.164us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 79.620s 2638.721us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 925.090s 31091.361us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 286.170s 7824.368us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 356.420s 9298.500us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 471.260s 8849.782us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1167.640s 28896.234us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 307.460s 7123.350us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 445.570s 7393.764us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 946.590s 11735.925us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 356.460s 5200.303us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 79.620s 2638.721us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 332.460s 6698.310us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 777.170s 14431.351us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 306.960s 6970.863us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 145.740s 3449.498us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 328.560s 7421.956us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 450.720s 7645.139us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1135.660s 15039.679us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2188.130s 40185.463us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 183.520s 3341.461us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 401.010s 6298.303us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 310.270s 9956.572us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 310.270s 9956.572us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1135.660s 15039.679us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 328.560s 7421.956us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 356.460s 5200.303us 1 1 100.00
chip_sw_pwrmgr_smoketest 268.740s 7501.152us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 452.880s 5825.833us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 332.000s 7681.179us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 248.920s 4670.506us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1088.740s 16114.048us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 137.730s 3280.388us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 401.010s 6298.303us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1302.570s 8717.334us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 384.690s 6160.638us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 429.980s 5170.161us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 155.730s 2931.696us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 157.900s 3358.158us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 332.000s 7681.179us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 332.000s 7681.179us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 141.340s 3992.714us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 1280.460s 15906.046us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1095.840s 16322.884us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 452.880s 5825.833us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 163.330s 3609.592us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 150.790s 3331.484us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 427.320s 5993.637us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 199.300s 6199.266us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 627.440s 5902.884us 1 1 100.00
chip_plic_all_irqs_10 312.440s 4800.769us 1 1 100.00
chip_plic_all_irqs_20 432.410s 4377.278us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 142.070s 2937.415us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 172.700s 3865.974us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3579.890s 17373.146us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 210.020s 3871.418us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 162.090s 3938.668us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 161.650s 3140.962us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 156.270s 4297.792us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 346.200s 5815.243us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 292.570s 4942.253us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 521.540s 11134.473us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 340.420s 9992.654us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 599.210s 12180.955us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 401.010s 6298.303us 1 1 100.00
chip_sw_data_integrity_escalation 471.960s 6722.161us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 450.720s 7645.139us 1 1 100.00
chip_sw_sysrst_ctrl_reset 964.730s 23495.251us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 178.200s 4009.612us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 192.390s 4115.012us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 318.190s 5008.015us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 964.730s 23495.251us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 964.730s 23495.251us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2593.640s 20915.749us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2593.640s 20915.749us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 258.420s 8035.624us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3038.640s 35946.950us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 148.800s 3963.791us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 126.230s 3391.315us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 224.050s 4629.228us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 309.850s 4289.354us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 909.460s 9010.474us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 6041.270s 32662.909us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2237.560s 13155.202us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 153.770s 3909.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 234.090s 3380.439us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 82.790s 3175.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 11585.930s 68945.585us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1291.940s 6496.892us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 639.970s 16304.625us 0 1 0.00
rom_e2e_jtag_debug_dev 241.000s 5286.354us 0 1 0.00
rom_e2e_jtag_debug_rma 202.100s 3487.203us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 89.790s 2968.595us 0 1 0.00
rom_e2e_jtag_inject_dev 128.440s 3751.072us 0 1 0.00
rom_e2e_jtag_inject_rma 82.860s 2809.276us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 139.287s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 292.900s 4194.863us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 364.410s 3212.764us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 886.220s 5657.913us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 737.740s 6579.172us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 275.360s 3366.724us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 654.390s 6338.435us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 81.810s 2835.518us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 197.060s 4315.767us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 297.990s 6177.968us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 237.810s 4475.555us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1135.660s 15039.679us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 639.970s 16304.625us 0 1 0.00
rom_e2e_jtag_debug_dev 241.000s 5286.354us 0 1 0.00
rom_e2e_jtag_debug_rma 202.100s 3487.203us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 187.440s 3867.748us 0 1 0.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 401.010s 6298.303us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5535.460s 38513.468us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5535.460s 38513.468us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 163.930s 4241.998us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 313.440s 5227.510us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3287.710s 18890.918us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 236.220s 4566.456us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 17.550s 10.100us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 9.410s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 149.370s 2805.895us 1 1 100.00
chip_sw_otp_ctrl_descrambling 167.760s 3272.643us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 199.330s 3907.226us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 6.990s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 200.210s 3866.505us 1 1 100.00
ate_bootstrap_flash_erase 702.720s 10010.380us 0 1 0.00
ate_bootstrap_one_frame 6683.870s 43257.424us 1 1 100.00
ate_bootstrap_disjoint 10083.780s 79415.954us 1 1 100.00

Error Messages

   Test seed line log context
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 110544874538958267671173784870347052817892278749007141090750020357700038364973 335
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 38027080918972456661551614497947462612272157897456797064179913098005174007531 322
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 107677444604549335034075875464744160357347362135949528946446083184133604607264 322
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 69319839179025129039017904655265285956701839101162051346156927916346218698850 308
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 63027464886231862691206467719649260742629222445667541561315350117904403522598 306
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 1170236595048365105296913329374680314947382391368013849811067512208521428191 306
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 97061957849105713513905975900319144716315628997612686992861052485136422284976 318
UVM_ERROR @ 7421.955500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7421.955500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 21880321879505675374804354719346777437877375189765084801614298652524410596160 317
UVM_ERROR @ 7123.350000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7123.350000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 85092836096998552140927731944885870353845763920500768425749459804348825880592 333
UVM_ERROR @ 9298.500000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9298.500000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 34475493964540631448848120847213873372733427644291174562086928246253616665920 342
UVM_ERROR @ 23495.251000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 23495.251000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 25274635617933881278137450432560603186965340710098671743940547071252836842242 322
UVM_ERROR @ 7393.764000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7393.764000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 115646434681049966428443914224840184268983287642196510396850401257168094179807 372
UVM_INFO @ 14206.658426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 76346153462729509395039219783123778818047172212788405491739847991765549705852 372
UVM_INFO @ 15742.645906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 109233612622027087373983483553977457623194489762489005238027876997605967756134 344
UVM_INFO @ 6810.247700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 3 test runs
chip_sw_hmac_oneshot 79099315118051067211343419459140980223001268177435450701260590974218064514706 333
UVM_INFO @ 12018.636943 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 4640367638391233395148309067969841477004452401445356709056350426170706274672 358
UVM_INFO @ 12026.735408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 3508986779391372575656435490591067069039081792077680794028826112942472616391 339
UVM_INFO @ 20018.695751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 61676614456345384815411241025943148259318892265066860046284088201949931761901 321
UVM_ERROR @ 3449.498250 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3449.498250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 48798797699679321833552638383130665006627185768768251111344886603112678172957 370
UVM_ERROR @ 14431.351244 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 14431.351244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:615) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 89804476315514391639642282602276949238941494754005624115163704191302181510155 225
TL item was: req: (cip_tl_seq_item@35007) { a_addr: 'h10650 a_data: 'h71e8cbbd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h30 a_opcode: 'h4 a_user: 'h19289 d_param: 'h0 d_source: 'h30 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3012.554777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 90345491927715085732766435473762693040782070546375039059071337509771056769705 245
TL item was: req: (cip_tl_seq_item@218110) { a_addr: 'h1036c a_data: 'h77329c99 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h1a2e9 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 7475.474177 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 77297600809845028330808603322531336109273342608696321321921632841152054476315 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 66928200918153682356069262314123663404816320336322378779807346974881404243338 None
Another command (pid=629163) is running. Waiting for it to complete on the server (server_pid=271672)...
Another command (pid=652744) is running. Waiting for it to complete on the server (server_pid=271672)...
Another command (pid=626367) is running. Waiting for it to complete on the server (server_pid=271672)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 88118107578706225423956158814900473827262312177653253619874767210976569720810 309
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 50128295350599508740737114709371621128761435054108267257375588986113006218674 335
UVM_INFO @ 3938.668248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 15436984522166331050344120728869229830319294305093450982876762067635186120463 312
UVM_INFO @ 2817.209734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 56187157574847182308608556147242518283637061410179703216412166062978310567385 350
UVM_INFO @ 10000.486483 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 16608999313198172519953567401724097981434013922218211367855913437824218037912 324
UVM_ERROR @ 4315.767292 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 4315.767292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 11394797510699139369555629035128075742452644193269810705497184949946586661273 285
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_transition 50069991182575052106384016521905407416111722984038431272344706187775118060195 313
UVM_INFO @ 27124.390630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 36041060141745103668636273471513527096927407834853134328352179322267623759252 311
UVM_ERROR @ 2638.721128 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2638.721128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 7945584547597121491509431132841568695319573975148062441558797200546382688482 335
UVM_INFO @ 35946.950219 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:381)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 115000599234546140093843593378257965987651328120251986179268148296673005283130 310
UVM_INFO @ 3926.844356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 88866283348645750003866515644104209882664143111299886901107733421722057414048 311
UVM_INFO @ 3188.353948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 39444587634590547985450947694249224546473516427092091159738497836763016500021 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 40343598164932635679620944131156908610694007579149352371303249851297160944316 346
UVM_INFO @ 4194.862701 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: jtag_dmi_ral.progbuf_* reset value: * straight after write. 1 test run
chip_sw_rv_dm_access_after_wakeup 13538098148915245057426293745259191602143072638170971773410856806531088865187 317
UVM_INFO @ 3331.483884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 88957067834299966882963848148936498449506595275897412851222804158299360816709 319
UVM_ERROR @ 3867.748006 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 3867.748006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 46692136338492047832000243144586278521910776615017017024932137859522047980865 239
UVM_INFO @ 6199.265986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 91203726431659152849831670569270578863926935656404531377958236385702972853131 326
UVM_INFO @ 15785.704218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 12840624471916039614970947451433962180336409461469251096032672247004071400943 345
UVM_INFO @ 15280.919962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 31245824039375745705193256445102645568500848144770841210966597715745333766251 330
UVM_INFO @ 12780.472654 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 97740571739574119979098464457186771523551198230640712468437214040455232562435 275
UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! 1 test run
rom_e2e_jtag_debug_test_unlocked0 18142124617894691554643707330476888479182234951475689707068991814871800841130 333
UVM_INFO @ 16304.624998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_no_meas 25265996062553377060231592154215153278543446866469643731218103744863748628805 322
UVM_INFO @ 18576.473302 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
rom_raw_unlock 108424717713083199095117309344314393069194161252270023522577674265569409547479 301
UVM_INFO @ 25939.707269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 24639399337508071936054737866750945643111037987809499100174221760742664934961 335
UVM_ERROR @ 5248.819752 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5248.819752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---