Simulation Results: clkmgr

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.63 %
  • code
  • 98.14 %
  • assert
  • 94.49 %
  • func
  • 85.25 %
  • line
  • 99.12 %
  • branch
  • 98.95 %
  • cond
  • 92.61 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.000s 57.389us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.830s 23.736us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.710s 28.089us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.130s 871.929us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.100s 43.174us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.990s 41.186us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.710s 28.089us 1 1 100.00
clkmgr_csr_aliasing 1.100s 43.174us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.710s 15.799us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.140s 106.177us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.930s 71.909us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.780s 87.246us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.000s 57.389us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 8.990s 1999.458us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.760s 1101.535us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 8.990s 1999.458us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 31.450s 7746.508us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.770s 13.753us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.460s 67.708us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.460s 67.708us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 23.736us 1 1 100.00
clkmgr_csr_rw 0.710s 28.089us 1 1 100.00
clkmgr_csr_aliasing 1.100s 43.174us 1 1 100.00
clkmgr_same_csr_outstanding 1.440s 253.441us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.830s 23.736us 1 1 100.00
clkmgr_csr_rw 0.710s 28.089us 1 1 100.00
clkmgr_csr_aliasing 1.100s 43.174us 1 1 100.00
clkmgr_same_csr_outstanding 1.440s 253.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.210s 640.234us 1 1 100.00
clkmgr_tl_intg_err 41.200s 10082.412us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.600s 294.940us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.600s 294.940us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.600s 294.940us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.600s 294.940us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 444.480s 200000.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 41.200s 10082.412us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 8.990s 1999.458us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.760s 1101.535us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.600s 294.940us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.070s 110.483us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.330s 181.739us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.780s 47.297us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.800s 23.895us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.740s 21.026us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.710s 28.089us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.210s 640.234us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 28.089us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.710s 28.089us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.210s 640.234us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.410s 388.008us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 34.580s 3845.116us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 60487610610826520376792339911456074720149965857292002195019625145134260919712 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 101523157960055534828653477619104979170414079104786779816836419648122395230058 181
UVM_INFO @ 10082411990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---