Simulation Results: edn/edn0

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.50 %
  • code
  • 80.37 %
  • assert
  • 96.75 %
  • func
  • 79.37 %
  • line
  • 97.55 %
  • branch
  • 91.49 %
  • cond
  • 85.95 %
  • toggle
  • 75.78 %
  • FSM
  • 51.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 52.777us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.010s 16.730us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.910s 20.376us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.460s 3097.770us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 127.763us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.450s 39.359us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.910s 20.376us 1 1 100.00
edn_csr_aliasing 1.200s 127.763us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.420s 289.072us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.420s 289.072us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.420s 289.072us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.010s 23.940us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.150s 73.687us 1 1 100.00
errs 1 1 100.00
edn_err 0.900s 72.763us 1 1 100.00
disable 2 2 100.00
edn_disable 1.150s 35.497us 1 1 100.00
edn_disable_auto_req_mode 1.360s 59.743us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.000s 388.636us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 55.805us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.060s 19.205us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.140s 473.562us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.140s 473.562us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.010s 16.730us 1 1 100.00
edn_csr_rw 0.910s 20.376us 1 1 100.00
edn_csr_aliasing 1.200s 127.763us 1 1 100.00
edn_same_csr_outstanding 0.940s 57.572us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.010s 16.730us 1 1 100.00
edn_csr_rw 0.910s 20.376us 1 1 100.00
edn_csr_aliasing 1.200s 127.763us 1 1 100.00
edn_same_csr_outstanding 0.940s 57.572us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.190s 422.626us 1 1 100.00
edn_tl_intg_err 1.730s 50.604us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 63.901us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.150s 73.687us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.190s 422.626us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.190s 422.626us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.190s 422.626us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.190s 422.626us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.150s 73.687us 1 1 100.00
edn_sec_cm 4.190s 422.626us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.150s 73.687us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.730s 50.604us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 30.970s 1859.869us 1 1 100.00