Simulation Results: edn/edn1

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.36 %
  • code
  • 82.70 %
  • assert
  • 98.70 %
  • func
  • 80.67 %
  • line
  • 97.88 %
  • branch
  • 92.64 %
  • cond
  • 90.92 %
  • toggle
  • 87.74 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 20.842us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.930s 28.143us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 30.861us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.660s 163.497us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.210s 34.730us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.340s 100.934us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 30.861us 1 1 100.00
edn_csr_aliasing 1.210s 34.730us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.980s 79.515us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.980s 79.515us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.980s 79.515us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.830s 47.118us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.190s 126.928us 1 1 100.00
errs 1 1 100.00
edn_err 0.700s 29.256us 1 1 100.00
disable 2 2 100.00
edn_disable 0.850s 13.116us 1 1 100.00
edn_disable_auto_req_mode 0.830s 81.408us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.450s 438.082us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 33.127us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 27.355us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.110s 118.485us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.110s 118.485us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.930s 28.143us 1 1 100.00
edn_csr_rw 0.770s 30.861us 1 1 100.00
edn_csr_aliasing 1.210s 34.730us 1 1 100.00
edn_same_csr_outstanding 0.830s 81.119us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.930s 28.143us 1 1 100.00
edn_csr_rw 0.770s 30.861us 1 1 100.00
edn_csr_aliasing 1.210s 34.730us 1 1 100.00
edn_same_csr_outstanding 0.830s 81.119us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.740s 691.715us 1 1 100.00
edn_tl_intg_err 1.830s 219.936us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 29.938us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.190s 126.928us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.740s 691.715us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.740s 691.715us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.740s 691.715us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.740s 691.715us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.190s 126.928us 1 1 100.00
edn_sec_cm 3.740s 691.715us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.190s 126.928us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.830s 219.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 42.530s 11168.347us 1 1 100.00