Simulation Results: entropy_src/rng_4bits

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 74.97 %
  • code
  • 88.90 %
  • assert
  • 84.89 %
  • func
  • 51.13 %
  • block
  • 94.49 %
  • line
  • 97.19 %
  • branch
  • 86.75 %
  • toggle
  • 75.84 %
  • FSM
  • 95.83 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 25.352us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 33.220us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 99.774us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 119.748us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 69.477us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 47.096us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 99.774us 1 1 100.00
entropy_src_csr_aliasing 3.000s 69.477us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 25.352us 1 1 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
entropy_src_fw_ov 123.000s 14061.969us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 123.000s 14061.969us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 91.000s 14083.681us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
entropy_src_intr 9.000s 544.974us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
entropy_src_functional_alerts 4.000s 356.888us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 185.000s 13248.882us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 131.025us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 3.000s 114.644us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 199.140us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 37.924us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 483.650us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 483.650us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 33.220us 1 1 100.00
entropy_src_csr_rw 1.000s 99.774us 1 1 100.00
entropy_src_csr_aliasing 3.000s 69.477us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 291.486us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 33.220us 1 1 100.00
entropy_src_csr_rw 1.000s 99.774us 1 1 100.00
entropy_src_csr_aliasing 3.000s 69.477us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 291.486us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 293.195us 1 1 100.00
entropy_src_tl_intg_err 3.000s 230.607us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
entropy_src_cfg_regwen 2.000s 38.871us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
entropy_src_fw_ov 123.000s 14061.969us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 131.025us 1 1 100.00
entropy_src_sec_cm 2.000s 293.195us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 131.025us 1 1 100.00
entropy_src_sec_cm 2.000s 293.195us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 19.000s 13868.100us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 131.025us 1 1 100.00
entropy_src_sec_cm 2.000s 293.195us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 131.025us 1 1 100.00
entropy_src_sec_cm 2.000s 293.195us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 131.025us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 356.888us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 230.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 57.000s 14151.312us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 12.000s 1347.069us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 88556876680775344264874514842740957275633739210640258824318944537177259185539 777
UVM_INFO @ 1347068806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 3101569495674308018589649637772466544139084455352537572733777086515108131449 113
UVM_INFO @ 47096308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---