Simulation Results: flash_ctrl

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.17 %
  • code
  • 92.80 %
  • assert
  • 94.55 %
  • func
  • 95.17 %
  • line
  • 95.87 %
  • branch
  • 96.73 %
  • cond
  • 93.05 %
  • toggle
  • 92.66 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 52.440s 44.223us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.290s 28.034us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 16.500s 232.360us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.200s 258.547us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 28.490s 1824.898us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 24.280s 4928.855us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.420s 48.549us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.200s 258.547us 1 1 100.00
flash_ctrl_csr_aliasing 24.280s 4928.855us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.540s 55.919us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.740s 23.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.760s 157.488us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 37.960s 352.462us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1183.520s 343368.286us 1 1 100.00
flash_ctrl_hw_rma_reset 493.770s 40124.912us 1 1 100.00
flash_ctrl_lcmgr_intg 5.690s 82.709us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1354.530s 355074.982us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 170.360s 1604.061us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.780s 37.462us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1666.150s 104814.601us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 61.840s 2280.566us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 12.720s 60.727us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.830s 30.682us 1 1 100.00
flash_ctrl_re_evict 14.400s 246.413us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 19.870s 30.790us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 19.870s 30.790us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 131.450s 20288.541us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 17.450s 3018.369us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 240.420s 140.996us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 386.110s 5068.149us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 315.710s 732.533us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 1273.820s 7559.507us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.660s 139.528us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 97.620s 1752.784us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.160s 21.312us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.880s 51.583us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 728.480s 1547.785us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 39.270s 2049.416us 1 1 100.00
flash_ctrl_otp_reset 56.540s 74.024us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1183.520s 343368.286us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 120.470s 6487.896us 1 1 100.00
flash_ctrl_intr_wr 41.590s 2505.881us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 125.000s 9517.560us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 101.170s 131414.401us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 37.640s 7417.060us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.640s 3921.938us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.680s 111.863us 1 1 100.00
flash_ctrl_ro_derr 75.480s 1361.289us 1 1 100.00
flash_ctrl_rw_derr 153.950s 25562.882us 1 1 100.00
flash_ctrl_derr_detect 105.870s 1423.880us 1 1 100.00
flash_ctrl_integrity 328.400s 16811.575us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.050s 53.222us 1 1 100.00
flash_ctrl_ro_serr 77.540s 3008.361us 1 1 100.00
flash_ctrl_rw_serr 109.800s 2001.444us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 48.630s 2398.377us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 36.830s 7627.510us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 104.690s 3424.071us 1 1 100.00
flash_ctrl_write_word_sweep 6.210s 45.168us 1 1 100.00
flash_ctrl_read_word_sweep 6.240s 31.308us 1 1 100.00
flash_ctrl_ro 70.920s 3909.950us 1 1 100.00
flash_ctrl_rw 253.280s 37514.958us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 24.730s 901.578us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 542.610s 41408.794us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 56.790s 10020.193us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 9.120s 41.085us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.550s 18.548us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.500s 73.373us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.500s 73.373us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.500s 232.360us 1 1 100.00
flash_ctrl_csr_rw 9.200s 258.547us 1 1 100.00
flash_ctrl_csr_aliasing 24.280s 4928.855us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.310s 37.596us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 16.500s 232.360us 1 1 100.00
flash_ctrl_csr_rw 9.200s 258.547us 1 1 100.00
flash_ctrl_csr_aliasing 24.280s 4928.855us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.310s 37.596us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 39.480s 82.806us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 39.480s 82.806us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 39.480s 82.806us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 39.480s 82.806us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 23.330s 480.306us 1 1 100.00
tl_intg_err 1 2 50.00
flash_ctrl_sec_cm 3891.820s 200000.000us 0 1 0.00
flash_ctrl_tl_intg_err 192.740s 446.495us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 192.740s 446.495us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 192.740s 446.495us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.830s 73.731us 1 1 100.00
flash_ctrl_wr_intg 6.600s 193.434us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 52.440s 44.223us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 56.540s 74.024us 1 1 100.00
flash_ctrl_disable 10.160s 21.312us 1 1 100.00
flash_ctrl_sec_info_access 33.230s 666.103us 1 1 100.00
flash_ctrl_connect 8.880s 51.583us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.260s 69.161us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.200s 258.547us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 39.480s 82.806us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.200s 258.547us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 39.480s 82.806us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.200s 258.547us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 39.480s 82.806us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.160s 21.312us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.830s 73.731us 1 1 100.00
flash_ctrl_access_after_disable 6.500s 25.274us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.760s 201.242us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.160s 21.312us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 17.450s 3018.369us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 253.280s 37514.958us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 109.800s 2001.444us 1 1 100.00
flash_ctrl_rw_derr 153.950s 25562.882us 1 1 100.00
flash_ctrl_integrity 328.400s 16811.575us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1183.520s 343368.286us 1 1 100.00
sec_cm_ctrl_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3891.820s 200000.000us 0 1 0.00
sec_cm_phy_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3891.820s 200000.000us 0 1 0.00
sec_cm_phy_prog_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3891.820s 200000.000us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 3891.820s 200000.000us 0 1 0.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 7.880s 863.202us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 5.910s 76.583us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.530s 156.180us 1 1 100.00
sec_cm_fifo_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 3891.820s 200000.000us 0 1 0.00
sec_cm_mem_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3891.820s 200000.000us 0 1 0.00
sec_cm_prog_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 3891.820s 200000.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.060s 78.908us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 228.700s 611.505us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 1 test run
flash_ctrl_sec_cm 12899429525100569164209901132701149290928455662439862581024806594177482983590 7318
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---