Simulation Results: hmac

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.68 %
  • code
  • 97.16 %
  • assert
  • 97.60 %
  • func
  • 44.28 %
  • line
  • 99.59 %
  • branch
  • 99.17 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.800s 1543.348us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.770s 22.920us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.670s 20.580us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.010s 4152.314us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.100s 721.941us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.400s 125.391us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.670s 20.580us 1 1 100.00
hmac_csr_aliasing 4.100s 721.941us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 31.660s 1200.116us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 70.270s 2628.516us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 192.920s 103437.553us 1 1 100.00
hmac_test_sha384_vectors 414.910s 18984.191us 1 1 100.00
hmac_test_sha512_vectors 19.020s 1329.933us 1 1 100.00
hmac_test_hmac256_vectors 6.780s 601.962us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 724.535us 1 1 100.00
hmac_test_hmac512_vectors 11.810s 513.036us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 12.010s 918.192us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 678.070s 133099.329us 1 1 100.00
error 1 1 100.00
hmac_error 73.830s 38219.646us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 98.730s 26629.727us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.800s 1543.348us 1 1 100.00
hmac_long_msg 31.660s 1200.116us 1 1 100.00
hmac_back_pressure 70.270s 2628.516us 1 1 100.00
hmac_datapath_stress 678.070s 133099.329us 1 1 100.00
hmac_burst_wr 12.010s 918.192us 1 1 100.00
hmac_stress_all 192.950s 25771.270us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.800s 1543.348us 1 1 100.00
hmac_long_msg 31.660s 1200.116us 1 1 100.00
hmac_back_pressure 70.270s 2628.516us 1 1 100.00
hmac_datapath_stress 678.070s 133099.329us 1 1 100.00
hmac_wipe_secret 98.730s 26629.727us 1 1 100.00
hmac_test_sha256_vectors 192.920s 103437.553us 1 1 100.00
hmac_test_sha384_vectors 414.910s 18984.191us 1 1 100.00
hmac_test_sha512_vectors 19.020s 1329.933us 1 1 100.00
hmac_test_hmac256_vectors 6.780s 601.962us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 724.535us 1 1 100.00
hmac_test_hmac512_vectors 11.810s 513.036us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.800s 1543.348us 1 1 100.00
hmac_long_msg 31.660s 1200.116us 1 1 100.00
hmac_back_pressure 70.270s 2628.516us 1 1 100.00
hmac_datapath_stress 678.070s 133099.329us 1 1 100.00
hmac_burst_wr 12.010s 918.192us 1 1 100.00
hmac_error 73.830s 38219.646us 1 1 100.00
hmac_wipe_secret 98.730s 26629.727us 1 1 100.00
hmac_test_sha256_vectors 192.920s 103437.553us 1 1 100.00
hmac_test_sha384_vectors 414.910s 18984.191us 1 1 100.00
hmac_test_sha512_vectors 19.020s 1329.933us 1 1 100.00
hmac_test_hmac256_vectors 6.780s 601.962us 1 1 100.00
hmac_test_hmac384_vectors 8.000s 724.535us 1 1 100.00
hmac_test_hmac512_vectors 11.810s 513.036us 1 1 100.00
hmac_stress_all 192.950s 25771.270us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 192.950s 25771.270us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.560s 37.669us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.590s 31.044us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.880s 905.754us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.880s 905.754us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.770s 22.920us 1 1 100.00
hmac_csr_rw 0.670s 20.580us 1 1 100.00
hmac_csr_aliasing 4.100s 721.941us 1 1 100.00
hmac_same_csr_outstanding 1.790s 531.276us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.770s 22.920us 1 1 100.00
hmac_csr_rw 0.670s 20.580us 1 1 100.00
hmac_csr_aliasing 4.100s 721.941us 1 1 100.00
hmac_same_csr_outstanding 1.790s 531.276us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.790s 377.967us 1 1 100.00
hmac_tl_intg_err 2.010s 90.786us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.010s 90.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.800s 1543.348us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.170s 864.076us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 42.500s 7638.818us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.790s 31.538us 1 1 100.00