Simulation Results: i2c

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.28 %
  • code
  • 78.04 %
  • assert
  • 97.25 %
  • func
  • 80.55 %
  • line
  • 96.38 %
  • branch
  • 92.26 %
  • cond
  • 84.86 %
  • toggle
  • 72.65 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
90.24%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 17.610s 4833.239us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 5.820s 1737.817us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.700s 88.308us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.640s 31.285us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.200s 164.320us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.360s 140.151us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.730s 158.125us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.640s 31.285us 1 1 100.00
i2c_csr_aliasing 1.360s 140.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 3.710s 181.208us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 3600.364s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 39.580s 7088.456us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.650s 87.563us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 113.550s 14721.371us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 41.150s 25801.211us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.840s 144.661us 1 1 100.00
i2c_host_fifo_fmt_empty 3.630s 1073.130us 1 1 100.00
i2c_host_fifo_reset_rx 5.400s 756.447us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 114.350s 11526.620us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 6.000s 673.624us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.680s 5.769us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.460s 1601.875us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 302.950s 106623.117us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.320s 747.207us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 12.040s 1166.042us 1 1 100.00
i2c_target_intr_smoke 2.200s 6281.129us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.880s 307.406us 1 1 100.00
i2c_target_fifo_reset_tx 0.800s 365.717us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 22.510s 20641.504us 1 1 100.00
i2c_target_stress_rd 12.040s 1166.042us 1 1 100.00
i2c_target_intr_stress_wr 89.960s 22293.457us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.220s 6802.898us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 88.770s 3659.241us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.920s 1560.437us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 1.690s 3020.533us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.130s 531.634us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.950s 585.453us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 39.580s 7088.456us 1 1 100.00
i2c_host_perf_precise 1.350s 350.647us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 6.000s 673.624us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.710s 112.133us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.740s 483.685us 1 1 100.00
i2c_target_nack_acqfull_addr 1.540s 1057.833us 1 1 100.00
i2c_target_nack_txstretch 1.010s 168.672us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 9.610s 515.508us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.530s 549.149us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.650s 38.560us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.740s 57.877us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.020s 28.635us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.020s 28.635us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.700s 88.308us 1 1 100.00
i2c_csr_rw 0.640s 31.285us 1 1 100.00
i2c_csr_aliasing 1.360s 140.151us 1 1 100.00
i2c_same_csr_outstanding 0.900s 226.913us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.700s 88.308us 1 1 100.00
i2c_csr_rw 0.640s 31.285us 1 1 100.00
i2c_csr_aliasing 1.360s 140.151us 1 1 100.00
i2c_same_csr_outstanding 0.900s 226.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.500s 86.708us 1 1 100.00
i2c_sec_cm 0.800s 47.256us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.500s 86.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 19.330s 582.294us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.810s 196.989us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 2.730s 168.530us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 49640665609631699586758831080313110586586837475970873369150426906910780195478 117
UVM_INFO @ 181208002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 71671026473261626450015665863808782112210955719389401864004814989770470375342 81
UVM_INFO @ 5769450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
i2c_host_stress_all_with_rand_reset 113488745276971605175413465405402904234489991335460781061657940999023241317263 109
UVM_INFO @ 582293573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 75575683061502137385136864274300299897770167954648284044647816708496253618104 83
UVM_INFO @ 168529924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
i2c_host_stress_all 16934331589229687853891863770485989310325136672638769473549097478185523741950 None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 81210379088643096715306282289131468165425485648216353539732916074184242817928 89
UVM_INFO @ 1601875222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 99388625558817259836768167606894343391122761480646233644727074153601821734172 83
UVM_INFO @ 196988961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---