Simulation Results: lc_ctrl/volatile_unlock_disabled

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.41 %
  • code
  • 84.47 %
  • assert
  • 94.83 %
  • func
  • 91.94 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.29 %
  • toggle
  • 87.66 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.230s 71.613us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.830s 17.201us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.760s 20.834us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.110s 84.537us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 16.970us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.140s 24.072us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.760s 20.834us 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 16.970us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.370s 53.746us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.420s 239.196us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 29.693us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.370s 178.577us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.150s 451.237us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_ctrl_prog_failure 1.370s 178.577us 1 1 100.00
lc_ctrl_errors 5.150s 451.237us 1 1 100.00
lc_ctrl_security_escalation 3.180s 1047.809us 1 1 100.00
lc_ctrl_jtag_state_failure 24.300s 5475.976us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.110s 232.277us 1 1 100.00
lc_ctrl_jtag_errors 17.560s 4393.311us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.730s 2249.628us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.940s 1193.029us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.110s 232.277us 1 1 100.00
lc_ctrl_jtag_errors 17.560s 4393.311us 1 1 100.00
lc_ctrl_jtag_access 1.580s 361.852us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.600s 2864.390us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.380s 622.898us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.300s 209.409us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.910s 669.263us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.820s 2772.099us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.910s 33.086us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.110s 871.098us 1 1 100.00
lc_ctrl_jtag_alert_test 0.900s 43.452us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.870s 893.608us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.780s 41.313us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 20.430s 2987.034us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.720s 176.781us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.190s 83.541us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.190s 83.541us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 17.201us 1 1 100.00
lc_ctrl_csr_rw 0.760s 20.834us 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 16.970us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.130s 203.117us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.830s 17.201us 1 1 100.00
lc_ctrl_csr_rw 0.760s 20.834us 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 16.970us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.130s 203.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.220s 153.847us 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 117.051us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 117.051us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.420s 239.196us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_ctrl_sec_cm 5.220s 153.847us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_ctrl_sec_cm 5.220s 153.847us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_ctrl_sec_cm 5.220s 153.847us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_ctrl_sec_cm 5.220s 153.847us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_ctrl_sec_cm 5.220s 153.847us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_ctrl_sec_cm 5.220s 153.847us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_ctrl_sec_cm 5.220s 153.847us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.770s 235.077us 1 1 100.00
lc_ctrl_sec_cm 5.220s 153.847us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.180s 1047.809us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.370s 53.746us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3.940s 1193.029us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.740s 1231.061us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.740s 1231.061us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.450s 1695.057us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.240s 893.779us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.240s 893.779us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 23.940s 2263.104us 1 1 100.00