Simulation Results: lc_ctrl/volatile_unlock_enabled

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.53 %
  • code
  • 84.08 %
  • assert
  • 94.69 %
  • func
  • 92.83 %
  • line
  • 97.13 %
  • branch
  • 93.37 %
  • cond
  • 79.20 %
  • toggle
  • 86.20 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.020s 67.892us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.770s 209.962us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.710s 45.399us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.190s 45.704us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 29.447us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.910s 62.625us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.710s 45.399us 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 29.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.620s 181.342us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.610s 694.795us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.770s 13.108us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.310s 108.411us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.630s 266.877us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_ctrl_prog_failure 1.310s 108.411us 1 1 100.00
lc_ctrl_errors 4.630s 266.877us 1 1 100.00
lc_ctrl_security_escalation 4.100s 315.896us 1 1 100.00
lc_ctrl_jtag_state_failure 17.180s 1321.759us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.020s 839.197us 1 1 100.00
lc_ctrl_jtag_errors 17.970s 39116.525us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.530s 111.948us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.830s 2663.316us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.020s 839.197us 1 1 100.00
lc_ctrl_jtag_errors 17.970s 39116.525us 1 1 100.00
lc_ctrl_jtag_access 1.870s 760.039us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.270s 731.432us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.400s 440.582us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.930s 35.165us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 2.930s 744.688us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.320s 4461.481us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.820s 49.402us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.820s 144.091us 1 1 100.00
lc_ctrl_jtag_alert_test 0.980s 109.147us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.210s 775.573us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.710s 14.131us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 11.110s 4978.392us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.790s 29.968us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.380s 120.272us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.380s 120.272us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 209.962us 1 1 100.00
lc_ctrl_csr_rw 0.710s 45.399us 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 29.447us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.100s 154.113us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.770s 209.962us 1 1 100.00
lc_ctrl_csr_rw 0.710s 45.399us 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 29.447us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.100s 154.113us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.770s 1157.811us 1 1 100.00
lc_ctrl_tl_intg_err 1.230s 50.025us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.230s 50.025us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.610s 694.795us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_ctrl_sec_cm 5.770s 1157.811us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_ctrl_sec_cm 5.770s 1157.811us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_ctrl_sec_cm 5.770s 1157.811us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_ctrl_sec_cm 5.770s 1157.811us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_ctrl_sec_cm 5.770s 1157.811us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_ctrl_sec_cm 5.770s 1157.811us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_ctrl_sec_cm 5.770s 1157.811us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.160s 2791.141us 1 1 100.00
lc_ctrl_sec_cm 5.770s 1157.811us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.100s 315.896us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.620s 181.342us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.830s 2663.316us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.820s 1179.823us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.820s 1179.823us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.510s 222.159us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.110s 381.980us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.110s 381.980us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 9.810s 3819.332us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 5559972031205677992679268606570711290244198353248234035569053202498479625719 2337
UVM_INFO @ 3819332227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---