Simulation Results: pwrmgr

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.62 %
  • code
  • 95.70 %
  • assert
  • 98.96 %
  • func
  • 98.19 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.90 %
  • toggle
  • 91.15 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.640s 24.789us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.690s 25.836us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.620s 51.735us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.810s 204.600us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.920s 35.590us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.860s 40.144us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.620s 51.735us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 35.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.750s 200.527us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.750s 200.527us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.920s 64.915us 1 1 100.00
pwrmgr_lowpower_invalid 0.730s 43.375us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.890s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.750s 118.429us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.890s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.840s 267.482us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.690s 153.015us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.700s 62.375us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.700s 933.064us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.570s 21.668us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.180s 271.932us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.180s 271.932us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.690s 25.836us 1 1 100.00
pwrmgr_csr_rw 0.620s 51.735us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 35.590us 1 1 100.00
pwrmgr_same_csr_outstanding 0.750s 45.096us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.690s 25.836us 1 1 100.00
pwrmgr_csr_rw 0.620s 51.735us 1 1 100.00
pwrmgr_csr_aliasing 0.920s 35.590us 1 1 100.00
pwrmgr_same_csr_outstanding 0.750s 45.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.210s 463.640us 1 1 100.00
pwrmgr_sec_cm 1.140s 927.686us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.140s 927.686us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.140s 927.686us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.210s 463.640us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.980s 800.581us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.840s 267.482us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.560s 869.345us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.750s 131.018us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.780s 39.301us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.140s 927.686us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.140s 927.686us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.140s 927.686us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.650s 25.620us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.700s 53.323us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.710s 225.352us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 51.735us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.620s 51.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.790s 319.144us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 8.100s 3582.149us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 107688307435615489824472807299262784969438963582228467498838293029837609685130 135
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 94924900377727091225790400644240503961128882996703098892483017878249577567095 79
UVM_ERROR @ 319144168 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 319144168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---