| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| rom_ctrl_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_max_throughput_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_err_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| rom_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| rom_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| passthru_mem_tl_intg_err | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_checker_fsm_local_esc | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctrl_flow_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_compare_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_digest | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_local_esc | 0 | 2 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_ctrl_kmac_err_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_mubi | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mux_consistency | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_mem_integrity | 0 | 1 | 0.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| rom_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 20 test runs | |||
| rom_ctrl_smoke | 53967098129483484045955939444758065762970396590721881042920967160075328403757 | None | ||
| rom_ctrl_stress_all | 42769552202352377131696085624594672623272952148174630669590946867025920851530 | None | ||
| rom_ctrl_max_throughput_chk | 20367962930114737671182962692837060361080825313697690042784281167105377651069 | None | ||
| rom_ctrl_corrupt_sig_fatal_chk | 81991187139355700701342831271890338332370547863362607600551229639333560082823 | None | ||
| rom_ctrl_kmac_err_chk | 103693738989676059016190555040413395785735288221557961994878123518467111786735 | None | ||
| rom_ctrl_stress_all_with_rand_reset | 90155338179276372497784498848920570093922706431874068464839637883980350298324 | None | ||
| rom_ctrl_sec_cm | 110958550100018176319421450840516155331327459327908194101209626728348227315575 | None | ||
| rom_ctrl_passthru_mem_tl_intg_err | 108959866179400753222550130527612673495050773189010420756902031844055308008863 | None | ||
| rom_ctrl_tl_errors | 101832061968302600247958858928497273309294853786794414149428410856244306312727 | None | ||
| rom_ctrl_tl_intg_err | 61831513969180221018880719109884828258338393525327624205448483959593795581551 | None | ||
| rom_ctrl_alert_test | 9694066877142444333993313839950181588228569863756833326584067496433880768676 | None | ||
| rom_ctrl_mem_walk | 61630223171909740587632095878499727472714041523637929914063187863510530477337 | None | ||
| rom_ctrl_mem_partial_access | 101348231469698592705189069806014462898664434380592949448753120863242944820780 | None | ||
| rom_ctrl_csr_hw_reset | 54873444729322427490354108711501289088674896818926387600513417622465078503894 | None | ||
| rom_ctrl_csr_rw | 27564815892396137278391174862413329059191726648551817759962823688197920418326 | None | ||
| rom_ctrl_csr_bit_bash | 106828839092506705045959461478833365636066627567491240556291220079226289655556 | None | ||
| rom_ctrl_csr_aliasing | 38978659103362933489131500721636023941314665793647487788898070613537261032356 | None | ||
| rom_ctrl_same_csr_outstanding | 19587762007783209089276379873723471197784838315908899799013656576402369739719 | None | ||
| rom_ctrl_csr_mem_rw_with_rand_reset | 52402091725397596968024463900236660819163285860997586304511746874762333867223 | None | ||
| rom_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/default/fusesoc-work/184236: No such file or directory.
/tmp/vcs_20260804153205_128873/.stack_annotator_gdb_cmd_file_Yy3gcE:2: Error in sourced command file:
No stack.
Process VmPeak: 437104 kb, VmSize: 421500 kb
System Free Memory: 164157892 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 11.590 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/cover_reg_top/fusesoc-work/105156: No such file or directory.
/tmp/vcs_20260804153103_10037/.stack_annotator_gdb_cmd_file_yKK47b:2: Error in sourced command file:
No stack.
Process VmPeak: 438004 kb, VmSize: 422400 kb
System Free Memory: 163125176 kb, System Free Swap: 0 kb
Completed context dump phase location* 'Module' 'Module'
CPU time: 12.735 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| rom_ctrl | None | None | ||