Simulation Results: spi_host

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.76 %
  • code
  • 91.30 %
  • assert
  • 94.90 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 34.000s 2105.726us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 20.085us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 16.687us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 1.000s 50.364us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 72.392us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 38.565us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 16.687us 1 1 100.00
spi_host_csr_aliasing 2.000s 72.392us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 14.900us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 16.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 37.924us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 204.787us 1 1 100.00
spi_host_error_cmd 1.000s 35.188us 1 1 100.00
spi_host_event 4.000s 1065.712us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 117.958us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 117.958us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 117.958us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 124.000s 7431.980us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 71.000s 3823.640us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 95.486us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 117.958us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 117.958us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 34.000s 2105.726us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 34.000s 2105.726us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 10.000s 734.331us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 185.174us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 62.000s 37316.231us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 1.000s 313.942us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 204.787us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 152.323us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 160.061us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 80.096us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 80.096us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 20.085us 1 1 100.00
spi_host_csr_rw 1.000s 16.687us 1 1 100.00
spi_host_csr_aliasing 2.000s 72.392us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 63.952us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 20.085us 1 1 100.00
spi_host_csr_rw 1.000s 16.687us 1 1 100.00
spi_host_csr_aliasing 2.000s 72.392us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 63.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 155.896us 1 1 100.00
spi_host_sec_cm 2.000s 74.669us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 155.896us 1 1 100.00