Simulation Results: sram_ctrl/main

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 95.49 %
  • assert
  • 97.82 %
  • func
  • 94.60 %
  • block
  • 95.82 %
  • line
  • 96.45 %
  • branch
  • 93.67 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 778.515us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 43.790us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.206us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 61.019us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 62.407us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 7.000s 709.345us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.206us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 62.407us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 116.000s 20748.479us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 43.000s 5251.008us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 24.000s 4847.908us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 70.000s 16313.329us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 149.000s 15176.016us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 60.000s 155243.424us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 51.000s 22284.572us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 17.000s 14417.995us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 355.875us 1 1 100.00
sram_ctrl_partial_access_b2b 255.000s 37729.147us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 3.000s 699.988us 1 1 100.00
sram_ctrl_throughput_w_partial_write 3.000s 754.389us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 2689.881us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 1047.827us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 689.777us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 11.000s 7391.200us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 15.038us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 66.838us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 66.838us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 43.790us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.206us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 62.407us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 35.327us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 43.790us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.206us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 62.407us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 35.327us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 78511.159us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 446.147us 1 1 100.00
sram_ctrl_tl_intg_err 4.000s 289.726us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 446.147us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 4.000s 289.726us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 1047.827us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 1047.827us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.206us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 17.000s 14417.995us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 17.000s 14417.995us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 17.000s 14417.995us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 51.000s 22284.572us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 709.224us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 78511.159us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 3703.118us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 778.515us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 778.515us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 17.000s 14417.995us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 446.147us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 51.000s 22284.572us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 446.147us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 446.147us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 778.515us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 446.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 16.000s 676.738us 1 1 100.00