Simulation Results: sysrst_ctrl

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.91 %
  • code
  • 94.39 %
  • assert
  • 94.92 %
  • func
  • 68.42 %
  • line
  • 97.71 %
  • branch
  • 97.85 %
  • cond
  • 95.00 %
  • toggle
  • 100.00 %
  • FSM
  • 81.41 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.510s 2127.492us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.810s 2519.078us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.750s 2417.344us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.970s 2542.686us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 7.600s 4032.799us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.280s 2034.862us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 102.720s 56111.261us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 1.890s 2744.038us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.970s 2132.798us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.280s 2034.862us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.890s 2744.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 39.900s 83384.970us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 51.110s 58184.985us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.870s 3483.416us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 5.550s 4572.338us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.480s 2553.862us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 2.200s 2126.019us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 1.790s 2861.500us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.420s 2636.468us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 7.150s 8695.054us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 22.300s 28765.665us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 15.760s 10416.640us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.650s 2027.797us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.150s 2025.024us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.560s 2116.101us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.560s 2116.101us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.600s 4032.799us 1 1 100.00
sysrst_ctrl_csr_rw 4.280s 2034.862us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.890s 2744.038us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.690s 4873.985us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.600s 4032.799us 1 1 100.00
sysrst_ctrl_csr_rw 4.280s 2034.862us 1 1 100.00
sysrst_ctrl_csr_aliasing 1.890s 2744.038us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 2.690s 4873.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 36.820s 42025.691us 1 1 100.00
sysrst_ctrl_tl_intg_err 10.700s 44296.543us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 10.700s 44296.543us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 3.440s 9867.382us 1 1 100.00