Simulation Results: uart

 
04/08/2026 15:30:33 DVSim: v1.50.0 sha: ff213b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.59 %
  • code
  • 92.49 %
  • assert
  • 97.12 %
  • func
  • 58.15 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.67 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.140s 264.566us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.890s 19.886us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.840s 19.632us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.090s 1051.247us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.800s 68.448us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.090s 87.436us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.840s 19.632us 1 1 100.00
uart_csr_aliasing 0.800s 68.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 1.750s 2403.387us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.140s 264.566us 1 1 100.00
uart_tx_rx 1.750s 2403.387us 1 1 100.00
parity_error 2 2 100.00
uart_intr 9.160s 47649.118us 1 1 100.00
uart_rx_parity_err 16.430s 17569.042us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 1.750s 2403.387us 1 1 100.00
uart_intr 9.160s 47649.118us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 6.450s 26100.542us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 105.020s 230312.288us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 26.650s 103177.426us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 9.160s 47649.118us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 9.160s 47649.118us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 9.160s 47649.118us 1 1 100.00
perf 1 1 100.00
uart_perf 325.990s 13178.094us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 13.970s 11293.680us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 13.970s 11293.680us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 3.100s 4106.511us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 27.770s 33832.977us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 11.790s 6738.775us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 5.840s 4837.715us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 308.270s 108296.393us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 708.300s 189098.983us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.760s 14.017us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.660s 14.997us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.720s 452.647us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.720s 452.647us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.890s 19.886us 1 1 100.00
uart_csr_rw 0.840s 19.632us 1 1 100.00
uart_csr_aliasing 0.800s 68.448us 1 1 100.00
uart_same_csr_outstanding 0.650s 16.961us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.890s 19.886us 1 1 100.00
uart_csr_rw 0.840s 19.632us 1 1 100.00
uart_csr_aliasing 0.800s 68.448us 1 1 100.00
uart_same_csr_outstanding 0.650s 16.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.100s 87.221us 1 1 100.00
uart_tl_intg_err 0.850s 60.114us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.850s 60.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 25.740s 4878.726us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 1 test run
uart_noise_filter 114026617386118343864925913360816117754550271829502365609271811729160010963920 75
UVM_ERROR @ 2716078456 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2716187548 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2723842170 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 2732933170 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0