Simulation Results

Simulation Results: adc_ctrl

05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
66.01 %

code
92.82 %

assert
92.06 %

func
13.14 %

line
98.16 %

branch
96.47 %

cond
85.94 %

toggle
99.76 %

FSM
83.78 %

Validation stages

V1		100.00%
V2		57.89%
V2S		100.00%
V3		0.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	1.890s	5971.174us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	2.060s	1130.955us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	1.340s	497.012us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	43.360s	43502.321us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	1.690s	448.850us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	0.720s	668.122us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	1.340s	497.012us	1	1	100.00
	adc_ctrl_csr_aliasing	1.690s	448.850us	1	1	100.00

11/19 passed

57.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	0.760s	379.250us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	1.170s	450.235us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	0.850s	427.211us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	0.650s	323.811us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.990s	296.198us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.830s	350.902us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	1.190s	448.812us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	0.650s	434.174us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	1.560s	3748.212us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	4.240s	28718.693us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	11.740s	60749.324us	1	1	100.00
stress_all				1	1	100.00
	adc_ctrl_stress_all	39.200s	104873.479us	1	1	100.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	1.050s	359.110us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	0.680s	506.616us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	1.240s	1439.970us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	1.240s	1439.970us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	2.060s	1130.955us	1	1	100.00
	adc_ctrl_csr_rw	1.340s	497.012us	1	1	100.00
	adc_ctrl_csr_aliasing	1.690s	448.850us	1	1	100.00
	adc_ctrl_same_csr_outstanding	5.720s	2510.024us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	2.060s	1130.955us	1	1	100.00
	adc_ctrl_csr_rw	1.340s	497.012us	1	1	100.00
	adc_ctrl_csr_aliasing	1.690s	448.850us	1	1	100.00
	adc_ctrl_same_csr_outstanding	5.720s	2510.024us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	5.790s	3835.986us	1	1	100.00
	adc_ctrl_tl_intg_err	2.760s	8897.241us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	2.760s	8897.241us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	adc_ctrl_stress_all_with_rand_reset	1.070s	1313.140us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				9 test runs
	adc_ctrl_filters_polled	65409435820414914291166241485003164622966689952595998293523471244421926477652	386	UVM_INFO @ 379249804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	78226329196090413592779596776968903009499004665198338574447829332728882301817	386	UVM_INFO @ 450235055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	15399433099385707673492047986011099138124695182488892256120663817569257720662	386	UVM_INFO @ 427211091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	100385491663605049434616114026131617735383600864667353632606665377222390192720	386	UVM_INFO @ 323810624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	35658109976856957261829565436093080450278864627551656353198116445554828421132	386	UVM_INFO @ 296197627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	73042959271826732523409576880145868189000981482067647586141327140835160148772	386	UVM_INFO @ 350901903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	99442831486327147275166153413904767768786336862367847003035660736024911746444	386	UVM_INFO @ 434173561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	76895667014429097944284463444675058831052394530389531098814454456573515788569	386	UVM_INFO @ 448812491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	25458566714880556438999559717498629427341286561433468922433109906719765879407	402	UVM_INFO @ 1313139992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---