Simulation Results: alert_handler

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.18 %
  • code
  • 88.27 %
  • assert
  • 97.82 %
  • func
  • 75.45 %
  • line
  • 99.66 %
  • branch
  • 98.28 %
  • cond
  • 91.20 %
  • toggle
  • 82.84 %
  • FSM
  • 69.35 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 22.580s 2486.745us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 7.710s 182.904us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.650s 781.284us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 376.260s 30813.373us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 88.520s 2177.021us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.350s 36.645us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.650s 781.284us 1 1 100.00
alert_handler_csr_aliasing 88.520s 2177.021us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 106.190s 12344.179us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 2.560s 106.828us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1284.290s 43349.969us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 50.940s 20883.553us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 22.580s 2486.745us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 20.730s 600.482us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 40.350s 2670.316us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 51.300s 4925.157us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1316.280s 69369.271us 1 1 100.00
alert_handler_lpg_stub_clk 1357.210s 266815.461us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 49.950s 2535.120us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.400s 765.128us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.140s 21.550us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.230s 14.084us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 5.860s 55.673us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 5.860s 55.673us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 7.710s 182.904us 1 1 100.00
alert_handler_csr_rw 3.650s 781.284us 1 1 100.00
alert_handler_csr_aliasing 88.520s 2177.021us 1 1 100.00
alert_handler_same_csr_outstanding 8.030s 96.509us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 7.710s 182.904us 1 1 100.00
alert_handler_csr_rw 3.650s 781.284us 1 1 100.00
alert_handler_csr_aliasing 88.520s 2177.021us 1 1 100.00
alert_handler_same_csr_outstanding 8.030s 96.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 117.130s 2722.203us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 117.130s 2722.203us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 117.130s 2722.203us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 117.130s 2722.203us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 953.560s 174480.259us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
alert_handler_tl_intg_err 30.990s 380.368us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 30.990s 380.368us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 117.130s 2722.203us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 22.580s 2486.745us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 22.580s 2486.745us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 22.580s 2486.745us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 22.580s 2486.745us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 50.940s 20883.553us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1316.280s 69369.271us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 50.940s 20883.553us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1284.290s 43349.969us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1284.290s 43349.969us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 8.160s 663.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 50.550s 4302.294us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 84676562386407788682248210418016707909562320644818551758021604063401715755278 174
UVM_INFO @ 765127520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 103563401290334284467301274873164951161961133910449130213805702775589081505608 98
UVM_INFO @ 4302294361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---