Simulation Results: clkmgr

 
05/08/2026 15:30:30 DVSim: v1.50.0 sha: 023bd59 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.78 %
  • code
  • 96.91 %
  • assert
  • 92.94 %
  • func
  • 82.50 %
  • line
  • 98.52 %
  • branch
  • 97.80 %
  • cond
  • 89.50 %
  • toggle
  • 98.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.840s 44.513us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.800s 68.721us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.800s 28.305us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 6.310s 853.982us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.610s 230.387us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.860s 22.816us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.800s 28.305us 1 1 100.00
clkmgr_csr_aliasing 1.610s 230.387us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.160s 93.753us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.780s 37.243us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.670s 17.306us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.680s 25.696us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.840s 44.513us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.130s 1767.762us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.440s 496.825us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.130s 1767.762us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 9.670s 3974.295us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.880s 87.641us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.460s 239.585us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.460s 239.585us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.800s 68.721us 1 1 100.00
clkmgr_csr_rw 0.800s 28.305us 1 1 100.00
clkmgr_csr_aliasing 1.610s 230.387us 1 1 100.00
clkmgr_same_csr_outstanding 1.070s 105.625us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.800s 68.721us 1 1 100.00
clkmgr_csr_rw 0.800s 28.305us 1 1 100.00
clkmgr_csr_aliasing 1.610s 230.387us 1 1 100.00
clkmgr_same_csr_outstanding 1.070s 105.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.930s 64.953us 0 1 0.00
clkmgr_tl_intg_err 33.860s 10049.189us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 787.240s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 787.240s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 787.240s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 787.240s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.320s 35.019us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 33.860s 10049.189us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.130s 1767.762us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.440s 496.825us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 787.240s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.710s 19.362us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.960s 94.382us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.960s 109.719us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.790s 61.041us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.740s 17.338us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.800s 28.305us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.930s 64.953us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 28.305us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 28.305us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.930s 64.953us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.050s 534.936us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 12.460s 2020.095us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 106730617191961783210446334529923592915606296621351471507029087905089799279904 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 29226099659909780795032988422490837931625778684759751233042631295074669285577 75
UVM_INFO @ 35018864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 6669726501784396063072238935602308858413249517624339309183469379944029638190 103
UVM_INFO @ 64953063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 86519956395453451032107973227651213865379167953720735972144373964783813803198 118
UVM_INFO @ 10049189481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---